+++ /dev/null
-From 53cb843fb86158bb034c539fb5dea73568a58f51 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index 30777f9f1a439..9c50b5a90e0b6 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2373,262 +2373,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3261,21 +3005,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
nfc-fdp-add-null-check-of-devm_kmalloc_array-in-fdp_.patch
ila-do-not-generate-empty-messages-in-ila_xlat_nl_cm.patch
net-caif-fix-use-after-free-in-cfusbl_device_notify.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
alpha-fix-r_alpha_literal-reloc-for-large-modules.patch
macintosh-windfarm-use-unsigned-type-for-1-bit-bitfi.patch
+++ /dev/null
-From 1cdec5bea8e734908046fba1eac013846203408b Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index 4ce1d7c88377f..e0fd37cb3eb50 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2371,262 +2371,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3259,21 +3003,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
kbuild-generate-modules.order-only-in-directories-vi.patch
scsi-core-remove-the-proc-scsi-proc_name-directory-e.patch
revert-spi-mt7621-fix-an-error-message-in-mt7621_spi_probe.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
alpha-fix-r_alpha_literal-reloc-for-large-modules.patch
macintosh-windfarm-use-unsigned-type-for-1-bit-bitfi.patch
+++ /dev/null
-From 68a13c891c6e3f22174885520459f88bcfd967c3 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index fbfcf00067394..893e5536f64c7 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2363,262 +2363,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3251,21 +2995,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
block-bfq-iosched.c-use-false-rather-than-blk_rw_asy.patch
block-bfq-replace-0-1-with-false-true-in-bic-apis.patch
block-bfq-fix-uaf-for-bfqq-in-bic_set_bfqq.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
powerpc-kcsan-exclude-udelay-to-prevent-recursive-in.patch
alpha-fix-r_alpha_literal-reloc-for-large-modules.patch
+++ /dev/null
-From ec29a899c35d83efe322cffd0eeebcf29ff8411c Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index fbfcf00067394..893e5536f64c7 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2363,262 +2363,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3251,21 +2995,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
attr-add-setattr_should_drop_sgid.patch
attr-use-consistent-sgid-stripping-checks.patch
fs-use-consistent-setgid-checks-in-is_sxid.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
powerpc-iommu-fix-memory-leak-with-using-debugfs_loo.patch
powerpc-kcsan-exclude-udelay-to-prevent-recursive-in.patch
+++ /dev/null
-From f636f5cb432828717f28873c99aa4a02b7f39936 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index fbfcf00067394..893e5536f64c7 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2363,262 +2363,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3251,21 +2995,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
net-smc-fix-fallback-failed-while-sendmsg-with-fasto.patch
riscv-use-read_once_nocheck-in-imprecise-unwinding-s.patch
ext4-fix-deadlock-during-directory-rename.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
alpha-fix-r_alpha_literal-reloc-for-large-modules.patch
macintosh-windfarm-use-unsigned-type-for-1-bit-bitfi.patch
+++ /dev/null
-From 2afdca4b124d5e436c550327e60b950350064462 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index e9f9713591558..025e21793b3c4 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2364,262 +2364,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3252,21 +2996,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
drm-msm-adreno-fix-runtime-pm-imbalance-at-unbind.patch
watch_queue-fix-ioc_watch_queue_set_size-alloc-error.patch
tpm-eventlog-don-t-abort-tpm_read_log-on-faulty-acpi.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
powerpc-64-don-t-recurse-irq-replay.patch
powerpc-iommu-fix-memory-leak-with-using-debugfs_loo.patch
+++ /dev/null
-From 0c14f1b6fb71eecf2741a96f578523ee87f28478 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Wed, 11 Jan 2023 08:04:00 +0200
-Subject: clk: qcom: mmcc-apq8084: remove spdm clocks
-
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-
-[ Upstream commit 7b347f4b677b6d84687e67d82b6b17c6f55ea2b4 ]
-
-SPDM is used for debug/profiling and does not have any other
-functionality. These clocks can safely be removed.
-
-Suggested-by: Stephen Boyd <sboyd@kernel.org>
-Suggested-by: Georgi Djakov <djakov@kernel.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20230111060402.1168726-11-dmitry.baryshkov@linaro.org
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/clk/qcom/mmcc-apq8084.c | 271 --------------------------------
- 1 file changed, 271 deletions(-)
-
-diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
-index e9f9713591558..025e21793b3c4 100644
---- a/drivers/clk/qcom/mmcc-apq8084.c
-+++ b/drivers/clk/qcom/mmcc-apq8084.c
-@@ -2364,262 +2364,6 @@ static struct clk_branch mmss_rbcpr_clk = {
- },
- };
-
--static struct clk_branch mmss_spdm_ahb_clk = {
-- .halt_reg = 0x0230,
-- .clkr = {
-- .enable_reg = 0x0230,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_ahb_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_ahb_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_axi_clk = {
-- .halt_reg = 0x0210,
-- .clkr = {
-- .enable_reg = 0x0210,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_axi_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_csi0_clk = {
-- .halt_reg = 0x023c,
-- .clkr = {
-- .enable_reg = 0x023c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_csi0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_csi0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_gfx3d_clk = {
-- .halt_reg = 0x022c,
-- .clkr = {
-- .enable_reg = 0x022c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_gfx3d_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_gfx3d_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg0_clk = {
-- .halt_reg = 0x0204,
-- .clkr = {
-- .enable_reg = 0x0204,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg1_clk = {
-- .halt_reg = 0x0208,
-- .clkr = {
-- .enable_reg = 0x0208,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_jpeg2_clk = {
-- .halt_reg = 0x0224,
-- .clkr = {
-- .enable_reg = 0x0224,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_jpeg2_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_jpeg2_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_mdp_clk = {
-- .halt_reg = 0x020c,
-- .clkr = {
-- .enable_reg = 0x020c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_mdp_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_mdp_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk0_clk = {
-- .halt_reg = 0x0234,
-- .clkr = {
-- .enable_reg = 0x0234,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_pclk1_clk = {
-- .halt_reg = 0x0228,
-- .clkr = {
-- .enable_reg = 0x0228,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_pclk1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_pclk1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vcodec0_clk = {
-- .halt_reg = 0x0214,
-- .clkr = {
-- .enable_reg = 0x0214,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vcodec0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vcodec0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe0_clk = {
-- .halt_reg = 0x0218,
-- .clkr = {
-- .enable_reg = 0x0218,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe0_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe0_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_vfe1_clk = {
-- .halt_reg = 0x021c,
-- .clkr = {
-- .enable_reg = 0x021c,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_vfe1_clk",
-- .parent_names = (const char *[]){
-- "mmss_spdm_vfe1_div_clk",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_axi_clk = {
-- .halt_reg = 0x0304,
-- .clkr = {
-- .enable_reg = 0x0304,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_axi_clk",
-- .parent_names = (const char *[]){
-- "mmss_axi_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
-- .halt_reg = 0x0308,
-- .clkr = {
-- .enable_reg = 0x0308,
-- .enable_mask = BIT(0),
-- .hw.init = &(struct clk_init_data){
-- .name = "mmss_spdm_rm_ocmemnoc_clk",
-- .parent_names = (const char *[]){
-- "ocmemnoc_clk_src",
-- },
-- .num_parents = 1,
-- .flags = CLK_SET_RATE_PARENT,
-- .ops = &clk_branch2_ops,
-- },
-- },
--};
--
--
- static struct clk_branch mmss_misc_ahb_clk = {
- .halt_reg = 0x502c,
- .clkr = {
-@@ -3252,21 +2996,6 @@ static struct clk_regmap *mmcc_apq8084_clocks[] = {
- [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
- [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
- [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
-- [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
-- [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
-- [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
-- [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
-- [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
-- [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
-- [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
-- [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
-- [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
-- [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
-- [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
-- [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
-- [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
-- [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
-- [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
- [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
- [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
- [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
---
-2.39.2
-
drm-amdgpu-soc21-add-video-cap-query-support-for-vcn.patch
watch_queue-fix-ioc_watch_queue_set_size-alloc-error.patch
tpm-eventlog-don-t-abort-tpm_read_log-on-faulty-acpi.patch
-clk-qcom-mmcc-apq8084-remove-spdm-clocks.patch
mips-fix-a-compilation-issue.patch
powerpc-64-don-t-recurse-irq-replay.patch
powerpc-iommu-fix-memory-leak-with-using-debugfs_loo.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
