drm/i915: Introduce i915_error_regs

Introduce i915_error_regs as the EIR/EMR counterpart
to the IIR/IMR/IER i915_irq_regs, and update the irq
reset/postingstall to utilize them accordingly.

v2: Include xe compat versions

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250217070047.953-7-ville.syrjala@linux.intel.com
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f98e5cc14724b64fcfdbe65913a30aea478bacfc..bba0a0acf0ae8aa0028335851e95e6802a08a640 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -120,6 +120,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
        intel_uncore_posting_read(uncore, regs.imr);
 }
 
+void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
+{
+       intel_uncore_write(uncore, regs.emr, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.emr);
+
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+}
+
+void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
+                    u32 emr_val)
+{
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+
+       intel_uncore_write(uncore, regs.emr, emr_val);
+       intel_uncore_posting_read(uncore, regs.emr);
+}
+
 /**
  * ivb_parity_work - Workqueue called when a parity error interrupt
  * occurred.
@@ -867,6 +890,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
 
        i9xx_display_irq_reset(dev_priv);
 
+       gen2_error_reset(uncore, GEN2_ERROR_REGS);
        gen2_irq_reset(uncore, GEN2_IRQ_REGS);
        dev_priv->irq_mask = ~0u;
 }
@@ -876,7 +900,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
        struct intel_uncore *uncore = &dev_priv->uncore;
        u32 enable_mask;
 
-       intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
+       gen2_error_init(uncore, GEN2_ERROR_REGS, i9xx_error_mask(dev_priv));
 
        dev_priv->irq_mask =
                ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@@ -972,6 +996,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
 
        i9xx_display_irq_reset(dev_priv);
 
+       gen2_error_reset(uncore, GEN2_ERROR_REGS);
        gen2_irq_reset(uncore, GEN2_IRQ_REGS);
        dev_priv->irq_mask = ~0u;
 }
@@ -1000,7 +1025,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
        struct intel_uncore *uncore = &dev_priv->uncore;
        u32 enable_mask;
 
-       intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
+       gen2_error_init(uncore, GEN2_ERROR_REGS, i965_error_mask(dev_priv));
 
        dev_priv->irq_mask =
                ~(I915_ASLE_INTERRUPT |

diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 0457f6402e051b765fb5fe1cf7cb0145cec00b2c..58789b264575cdb51a5219640f635d5f8246c2ec 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -47,4 +47,8 @@ void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
 void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
                   u32 imr_val, u32 ier_val);
 
+void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs);
+void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
+                    u32 emr_val);
+
 #endif /* __I915_IRQ_H__ */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e91fcf40a0f63dd6ed671423ae419d27fcf5d17..be1aab838be969fb46398c44366a740e9fbe3a7e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -472,6 +472,9 @@
 #define   GM45_ERROR_CP_PRIV                           (1 << 3)
 #define   I915_ERROR_MEMORY_REFRESH                    (1 << 1)
 #define   I915_ERROR_INSTRUCTION                       (1 << 0)
+
+#define GEN2_ERROR_REGS                I915_ERROR_REGS(EMR, EIR)
+
 #define INSTPM         _MMIO(0x20c0)
 #define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
 #define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts

diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index e251bcc0c89f5710125bc70f07851b2cb978c89c..94a8f902689e860b8226cc79a9974661318a39fe 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -294,4 +294,12 @@ struct i915_irq_regs {
 #define I915_IRQ_REGS(_imr, _ier, _iir) \
        ((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
 
+struct i915_error_regs {
+       i915_reg_t emr;
+       i915_reg_t eir;
+};
+
+#define I915_ERROR_REGS(_emr, _eir) \
+       ((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) })
+
 #endif /* __I915_REG_DEFS__ */

diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c
index ac4cda2d81c7a1fa5b707cd1af98283bd03e3d71..3c6bca66ddab6da9a63bb7d1aebe97aedad16f93 100644 (file)
--- a/drivers/gpu/drm/xe/display/ext/i915_irq.c
+++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c
@@ -51,6 +51,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
        intel_uncore_posting_read(uncore, regs.imr);
 }
 
+void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
+{
+       intel_uncore_write(uncore, regs.emr, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.emr);
+
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+}
+
+void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
+                    u32 emr_val)
+{
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+       intel_uncore_write(uncore, regs.eir, 0xffffffff);
+       intel_uncore_posting_read(uncore, regs.eir);
+
+       intel_uncore_write(uncore, regs.emr, emr_val);
+       intel_uncore_posting_read(uncore, regs.emr);
+}
+
 bool intel_irqs_enabled(struct xe_device *xe)
 {
        return atomic_read(&xe->irq.enabled);