drm/msm/dpu: enable writeback on SM8150

Enable WB2 hardware block, enabling writeback support on this platform.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570192/
Link: https://lore.kernel.org/r/20231203003203.1293087-2-dmitry.baryshkov@linaro.org
[DB: picked up WB_SDM845_MASK from sdm845 patch]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 145f3d5953a30de0c847bc7800f3661a33c67ac7..6ccfde82fecdb4e3612df161814b16f7af40ca5f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -33,6 +33,7 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
                [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
                [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
                [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+               [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
        },
 };
 
@@ -290,6 +291,21 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
        },
 };
 
+static const struct dpu_wb_cfg sm8150_wb[] = {
+       {
+               .name = "wb_2", .id = WB_2,
+               .base = 0x65000, .len = 0x2c8,
+               .features = WB_SDM845_MASK,
+               .format_list = wb2_formats_rgb,
+               .num_formats = ARRAY_SIZE(wb2_formats_rgb),
+               .clk_ctrl = DPU_CLK_CTRL_WB2,
+               .xin_id = 6,
+               .vbif_idx = VBIF_RT,
+               .maxlinewidth = 4096,
+               .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+       },
+};
+
 static const struct dpu_intf_cfg sm8150_intf[] = {
        {
                .name = "intf_0", .id = INTF_0,
@@ -384,6 +400,8 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
        .pingpong = sm8150_pp,
        .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
        .merge_3d = sm8150_merge_3d,
+       .wb_count = ARRAY_SIZE(sm8150_wb),
+       .wb = sm8150_wb,
        .intf_count = ARRAY_SIZE(sm8150_intf),
        .intf = sm8150_intf,
        .vbif_count = ARRAY_SIZE(sdm845_vbif),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 648c8d0a4c362d46eec87b47b733fc201c925379..dcb4fd85e73b9cc05e669043602d69229881c0b4 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -96,14 +96,16 @@
 
 #define INTF_SC7280_MASK (INTF_SC7180_MASK)
 
-#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
+#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
                         BIT(DPU_WB_UBWC) | \
                         BIT(DPU_WB_YUV_CONFIG) | \
                         BIT(DPU_WB_PIPE_ALPHA) | \
                         BIT(DPU_WB_XY_ROI_OFFSET) | \
                         BIT(DPU_WB_QOS) | \
                         BIT(DPU_WB_QOS_8LVL) | \
-                        BIT(DPU_WB_CDP) | \
+                        BIT(DPU_WB_CDP))
+
+#define WB_SM8250_MASK (WB_SDM845_MASK | \
                         BIT(DPU_WB_INPUT_CTRL))
 
 #define DEFAULT_PIXEL_RAM_SIZE         (50 * 1024)