watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

Fix the PMU register bits for the ExynosAutoV920 SoC.
This SoC has different bit information compared to its previous
version, ExynosAutoV9, and we have made the necessary adjustments.

rst_stat_bit:
    - ExynosAutoV920 cl0 : 0
    - ExynosAutoV920 cl1 : 1

cnt_en_bit:
    - ExynosAutoV920 cl0 : 8
    - ExynosAutoV920 cl1 : 8

Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20250213004104.3881711-1-sw617.shin@samsung.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 30450e99e5e9d40b5596e2f87cc47c80ccbd2ddd..bdd81d8074b2496d68c2b0f086f477dc8652e452 100644 (file)
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -72,6 +72,8 @@
 #define EXYNOS850_CLUSTER1_WDTRESET_BIT                23
 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT     25
 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT     24
+#define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT   0
+#define EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT   1
 
 #define GS_CLUSTER0_NONCPU_OUT                 0x1220
 #define GS_CLUSTER1_NONCPU_OUT                 0x1420
@@ -312,9 +314,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
        .mask_bit = 2,
        .mask_reset_inv = true,
        .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
+       .rst_stat_bit = EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT,
        .cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
-       .cnt_en_bit = 7,
+       .cnt_en_bit = 8,
        .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
                  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
                  QUIRK_HAS_DBGACK_BIT,
@@ -325,9 +327,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
        .mask_bit = 2,
        .mask_reset_inv = true,
        .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
+       .rst_stat_bit = EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT,
        .cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
-       .cnt_en_bit = 7,
+       .cnt_en_bit = 8,
        .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
                  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
                  QUIRK_HAS_DBGACK_BIT,