drm/amdgpu: Check RRMT status for VCN v4.0.3

RRMT could get dynamically enabled/disabled by PSP firmware. Read the
status from register for reading RRMT status. For VFs, this is not
accessible, hence assume that it's always disabled for now.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index adaf4388ad2806f72fad1142e167541ecf556d81..c92f683ee5958a6bfbc73e195f132fd376b3b25f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -238,6 +238,12 @@
 
 #define AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING 2
 
+enum amdgpu_vcn_caps {
+       AMDGPU_VCN_RRMT_ENABLED,
+};
+
+#define AMDGPU_VCN_CAPS(caps) BIT(AMDGPU_VCN_##caps)
+
 enum fw_queue_mode {
        FW_QUEUE_RING_RESET = 1,
        FW_QUEUE_DPG_HOLD_OFF = 2,
@@ -345,6 +351,7 @@ struct amdgpu_vcn {
        uint32_t                *ip_dump;
 
        uint32_t                supported_reset;
+       uint32_t                caps;
 };
 
 struct amdgpu_fw_shared_rb_ptrs_struct {

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index ecdc027f822037ec150aa1d9d57841b67b9fc951..f0716c10f23e4a4f6ec7e041657b53db9ea0673c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -98,8 +98,7 @@ static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
 
 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev)
 {
-       return (amdgpu_sriov_vf(adev) ||
-               (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)));
+       return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0;
 }
 
 /**
@@ -295,6 +294,11 @@ static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
                        ring->sched.ready = true;
                }
        } else {
+               /* This flag is not set for VF, assumed to be disabled always */
+               if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) &
+                   0x100)
+                       adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED);
+
                for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
                        struct amdgpu_vcn4_fw_shared *fw_shared;