drm/amdgpu/gfx9: properly handle error ints on all pipes

Need to handle the interrupt enables for all pipes.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index d4e38edc9353bcb957bf4950a2992cb545b34dc2..97476fb2ca4080e2d45348de178b549d9ee7545b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2634,7 +2634,7 @@ static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
        tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
-       if(adev->gfx.num_gfx_rings)
+       if (adev->gfx.num_gfx_rings)
                tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
 
        WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
@@ -5929,17 +5929,59 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
        }
 }
 
+static u32 gfx_v9_0_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                    int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
+       case 2:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
+       case 3:
+               return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                             struct amdgpu_irq_src *source,
                                             unsigned type,
                                             enum amdgpu_interrupt_state state)
 {
+       u32 cp_int_cntl_reg, cp_int_cntl;
+       int i, j;
+
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
        case AMDGPU_IRQ_STATE_ENABLE:
                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
                               PRIV_REG_INT_ENABLE,
                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+               for (i = 0; i < adev->gfx.mec.num_mec; i++) {
+                       for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) {
+                               /* MECs start at 1 */
+                               cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j);
+
+                               if (cp_int_cntl_reg) {
+                                       cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
+                                       cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                   PRIV_REG_INT_ENABLE,
+                                                                   state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                       WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
+                               }
+                       }
+               }
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 2ac398184e1251e5c956ea20ab29a507704e404f..43a3ef276b5f376153f782528e4c808e59366f6d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2899,21 +2899,63 @@ static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
        }
 }
 
+static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev,
+                                    int xcc_id, int me, int pipe)
+{
+       /*
+        * amdgpu controls only the first MEC. That's why this function only
+        * handles the setting of interrupts for this specific MEC. All other
+        * pipes' interrupts are set by amdkfd.
+        */
+       if (me != 1)
+               return 0;
+
+       switch (pipe) {
+       case 0:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
+       case 1:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
+       case 2:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
+       case 3:
+               return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
+       default:
+               return 0;
+       }
+}
+
 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
                                             struct amdgpu_irq_src *source,
                                             unsigned type,
                                             enum amdgpu_interrupt_state state)
 {
-       int i, num_xcc;
+       u32 mec_int_cntl_reg, mec_int_cntl;
+       int i, j, k, num_xcc;
 
        num_xcc = NUM_XCC(adev->gfx.xcc_mask);
        switch (state) {
        case AMDGPU_IRQ_STATE_DISABLE:
        case AMDGPU_IRQ_STATE_ENABLE:
-               for (i = 0; i < num_xcc; i++)
+               for (i = 0; i < num_xcc; i++) {
                        WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
-                               PRIV_REG_INT_ENABLE,
-                               state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                                             PRIV_REG_INT_ENABLE,
+                                             state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+                       for (j = 0; j < adev->gfx.mec.num_mec; j++) {
+                               for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
+                                       /* MECs start at 1 */
+                                       mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k);
+
+                                       if (mec_int_cntl_reg) {
+                                               mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i);
+                                               mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
+                                                                            PRIV_REG_INT_ENABLE,
+                                                                            state == AMDGPU_IRQ_STATE_ENABLE ?
+                                                                            1 : 0);
+                                               WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i);
+                                       }
+                               }
+                       }
+               }
                break;
        default:
                break;