re PR target/91719 (gcc compiles seq_cst store on x86-64 differently from clang/icc)

	PR target/91719
	* config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro.
	* config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New.
	* config/i386/sync.md (atomic_store<mode>): emit XCHG for
	TARGET_USE_XCHG_FOR_ATOMIC_STORE.

From-SVN: r275754

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 63fae8615e5bd2b8f0ecb160ebe332f81ab4be7f..2f4de49fe8569400f4c235e46ab0dacb0daba2d1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-09-16  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/91719
+       * config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro.
+       * config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New.
+       * config/i386/sync.md (atomic_store<mode>): emit XCHG for
+       TARGET_USE_XCHG_FOR_ATOMIC_STORE.
+
 2019-09-16  Jason Merrill  <jason@redhat.com>
 
        * Makefile.in (build/genmatch.o): Depend on $(CPPLIB_H).

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index a1d0484d71fed80b57e3857ccb61577b6171c1a9..885846e0a351fbf6d389fb6dd5724d3f1e59a041 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -590,6 +590,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
        ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
 #define TARGET_ONE_IF_CONV_INSN \
        ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
+#define TARGET_USE_XCHG_FOR_ATOMIC_STORE \
+       ix86_tune_features[X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE]
 #define TARGET_EMIT_VZEROUPPER \
        ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
 

diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index ba146e3c8f8102b3dc4a19983d3b954ae06b08aa..2614ddb715ab912f37ca4175da33d6bf76e658bf 100644 (file)
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -306,8 +306,11 @@
     {
       operands[1] = force_reg (<MODE>mode, operands[1]);
 
-      /* For seq-cst stores, when we lack MFENCE, use XCHG.  */
-      if (is_mm_seq_cst (model) && !(TARGET_64BIT || TARGET_SSE2))
+      /* For seq-cst stores, use XCHG
+        when we lack MFENCE or when target prefers XCHG.  */
+      if (is_mm_seq_cst (model)
+         && (!(TARGET_64BIT || TARGET_SSE2)
+             || TARGET_USE_XCHG_FOR_ATOMIC_STORE))
        {
          emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode),
                                                operands[0], operands[1],

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index fd59a842658bc1520796f400c853467df8f49faa..e289efdf2e0c34b856566807efd3a9625628d237 100644 (file)
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -313,6 +313,10 @@ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
          m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
          | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
 
+/* X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE: Use xchg instead of mov+mfence.  */
+DEF_TUNE (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE, "use_xchg_for_atomic_store",
+        m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
+
 /*****************************************************************************/
 /* 387 instruction selection tuning                                          */
 /*****************************************************************************/