arm64: dts: amlogic: Add cache information to the Amlogic S7 SoC

As per S7 datasheet add missing cache information to the Amlogic S7 SoC.

 ARM Cortex-A55 CPU uses unified L2 cache.

- Each Cortex-A55 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 256KB Unified L2 cache.

Cache memory significantly reduces the time it takes for the CPU
to access data and instructions, leading to faster program execution
and overall system responsiveness.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250825065240.22577-10-linux.amoon@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index 260918b37b9ae283fb2e0f863997f507e0a7463a..d262c0b66e4b52afe1986864a27af19842a25a6b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -18,6 +18,13 @@
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
                };
 
                cpu1: cpu@100 {
@@ -25,6 +32,13 @@
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
                };
 
                cpu2: cpu@200 {
@@ -32,6 +46,13 @@
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x200>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
                };
 
                cpu3: cpu@300 {
@@ -39,8 +60,23 @@
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x300>;
                        enable-method = "psci";
+                       d-cache-line-size = <32>;
+                       d-cache-size = <0x8000>;
+                       d-cache-sets = <32>;
+                       i-cache-line-size = <32>;
+                       i-cache-size = <0x8000>;
+                       i-cache-sets = <32>;
+                       next-level-cache = <&l2>;
                };
 
+               l2: l2-cache0 {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
+                       cache-size = <0x40000>; /* L2. 256 KB */
+                       cache-line-size = <64>;
+                       cache-sets = <512>;
+               };
        };
 
        timer {