pinctrl: renesas: r8a779g0: Fix FXR_TXEN[AB] suffixes

The Pin Multiplex attachment in Rev.1.10 of the R-Car V4H Series
Hardware User's Manual still has two alternate pins named both
"FXR_TXEN[AB]".  To differentiate, the pin control driver uses
"FXR_TXEN[AB]" and "FXR_TXEN[AB]_X", which were considered temporary
names until the conflict was sorted out.

Fix this by adopting R-Car V4M naming:
  - Rename "FXR_TXEN[AB]" to "FXR_TXEN[AB]_A",
  - Rename "FXR_TXEN[AB]_X" to "FXR_TXEN[AB]_B".

Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support")
Fixes: 1c2646b5cebfff07 ("pinctrl: renesas: r8a779g0: Add missing FlexRay")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/5e1e9abb46c311d4c54450d991072d6d0e66f14c.1717754960.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index d90ba8b6b4b423ed783bb97caf39db868f493f28..ba2ec8e0421199b048a7ea7677119c2a9fefa65e 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -122,11 +122,11 @@
 #define GPSR2_8                F_(TPU0TO0,             IP1SR2_3_0)
 #define GPSR2_7                F_(TPU0TO1,             IP0SR2_31_28)
 #define GPSR2_6                F_(FXR_TXDB,            IP0SR2_27_24)
-#define GPSR2_5                F_(FXR_TXENB_N,         IP0SR2_23_20)
+#define GPSR2_5                F_(FXR_TXENB_N_A,       IP0SR2_23_20)
 #define GPSR2_4                F_(RXDB_EXTFXR,         IP0SR2_19_16)
 #define GPSR2_3                F_(CLK_EXTFXR,          IP0SR2_15_12)
 #define GPSR2_2                F_(RXDA_EXTFXR,         IP0SR2_11_8)
-#define GPSR2_1                F_(FXR_TXENA_N,         IP0SR2_7_4)
+#define GPSR2_1                F_(FXR_TXENA_N_A,       IP0SR2_7_4)
 #define GPSR2_0                F_(FXR_TXDA,            IP0SR2_3_0)
 
 /* GPSR3 */
@@ -340,18 +340,18 @@
 /* SR2 */
 /* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
 #define IP0SR2_3_0     FM(FXR_TXDA)            FM(CANFD1_TX)           FM(TPU0TO2_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_7_4     FM(FXR_TXENA_N)         FM(CANFD1_RX)           FM(TPU0TO3_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4     FM(FXR_TXENA_N_A)       FM(CANFD1_RX)           FM(TPU0TO3_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX_A)         FM(IRQ5)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX_A)         FM(IRQ4_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_19_16   FM(RXDB_EXTFXR)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_23_20   FM(FXR_TXENB_N)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_23_20   FM(FXR_TXENB_N_A)       F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_27_24   FM(FXR_TXDB)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_31_28   FM(TPU0TO1)             FM(CANFD6_TX)           F_(0, 0)                FM(TCLK2_B)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 
 /* IP1SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
 #define IP1SR2_3_0     FM(TPU0TO0)             FM(CANFD6_RX)           F_(0, 0)                FM(TCLK1_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_7_4     FM(CAN_CLK)             FM(FXR_TXENA_N_X)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_11_8    FM(CANFD0_TX)           FM(FXR_TXENB_N_X)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4     FM(CAN_CLK)             FM(FXR_TXENA_N_B)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8    FM(CANFD0_TX)           FM(FXR_TXENB_N_B)       F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_15_12   FM(CANFD0_RX)           FM(STPWT_EXTFXR)        F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_19_16   FM(CANFD2_TX)           FM(TPU0TO2)             F_(0, 0)                FM(TCLK3_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1SR2_23_20   FM(CANFD2_RX)           FM(TPU0TO3)             FM(PWM1_B)              FM(TCLK4_A)     F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -891,7 +891,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP0SR2_3_0,    CANFD1_TX),
        PINMUX_IPSR_GPSR(IP0SR2_3_0,    TPU0TO2_A),
 
-       PINMUX_IPSR_GPSR(IP0SR2_7_4,    FXR_TXENA_N),
+       PINMUX_IPSR_GPSR(IP0SR2_7_4,    FXR_TXENA_N_A),
        PINMUX_IPSR_GPSR(IP0SR2_7_4,    CANFD1_RX),
        PINMUX_IPSR_GPSR(IP0SR2_7_4,    TPU0TO3_A),
 
@@ -905,7 +905,7 @@ static const u16 pinmux_data[] = {
 
        PINMUX_IPSR_GPSR(IP0SR2_19_16,  RXDB_EXTFXR),
 
-       PINMUX_IPSR_GPSR(IP0SR2_23_20,  FXR_TXENB_N),
+       PINMUX_IPSR_GPSR(IP0SR2_23_20,  FXR_TXENB_N_A),
 
        PINMUX_IPSR_GPSR(IP0SR2_27_24,  FXR_TXDB),
 
@@ -919,10 +919,10 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP1SR2_3_0,    TCLK1_A),
 
        PINMUX_IPSR_GPSR(IP1SR2_7_4,    CAN_CLK),
-       PINMUX_IPSR_GPSR(IP1SR2_7_4,    FXR_TXENA_N_X),
+       PINMUX_IPSR_GPSR(IP1SR2_7_4,    FXR_TXENA_N_B),
 
        PINMUX_IPSR_GPSR(IP1SR2_11_8,   CANFD0_TX),
-       PINMUX_IPSR_GPSR(IP1SR2_11_8,   FXR_TXENB_N_X),
+       PINMUX_IPSR_GPSR(IP1SR2_11_8,   FXR_TXENB_N_B),
 
        PINMUX_IPSR_GPSR(IP1SR2_15_12,  CANFD0_RX),
        PINMUX_IPSR_GPSR(IP1SR2_15_12,  STPWT_EXTFXR),