amdgcn: Fix various unrecognized pattern issues with add<mode>3_vcc_dup

The patterns did not accept inline immediate constants, even though the
hardware instructions do, which has lead to some errors in some patches I'm
working on.

Also the VCC update RTL was using the wrong operands in the wrong places.  This
appears to have been harmless(?) but is definitely not intended.

gcc/ChangeLog:

	* config/gcn/gcn-valu.md (add<mode>3_vcc_dup<exec_vcc>): Change
	operand 2 to allow gcn_alu_operand.  Swap the operands in the VCC
	update RTL.
	(add<mode>3_vcc_zext_dup): Likewise.
	(add<mode>3_vcc_zext_dup_exec): Likewise.
	(add<mode>3_vcc_zext_dup2): Likewise.
	(add<mode>3_vcc_zext_dup2_exec): Likewise.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 71a3916d0a1ede2cfc4b476dd88b6733725e89a0..7c4dde1cfce49ae61084d0454758046d03de3081 100644 (file)
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -1501,16 +1501,16 @@
        (plus:V_SI
          (vec_duplicate:V_SI
            (match_operand:SI 1 "gcn_alu_operand"))
-         (match_operand:V_SI 2 "register_operand")))
+         (match_operand:V_SI 2 "gcn_alu_operand")))
    (set (match_operand:DI 3 "register_operand")
-       (ltu:DI (plus:V_SI (vec_duplicate:V_SI (match_dup 2))
-                          (match_dup 1))
-               (vec_duplicate:V_SI (match_dup 2))))]
+       (ltu:DI (plus:V_SI (vec_duplicate:V_SI (match_dup 1))
+                          (match_dup 2))
+               (match_dup 2)))]
   ""
   {@ [cons: =0, 1, 2, =3; attrs: type, length]
-  [v,SvA,v,cV;vop2 ,4] v_add_co_u32\t%0, %3, %1, %2
-  [v,SvB,v,cV;vop2 ,8] ^
-  [v,SvA,v,Sg;vop3b,8] ^
+  [v,SvA,vA,cV;vop2 ,4] v_add_co_u32\t%0, %3, %1, %2
+  [v,SvB,vA,cV;vop2 ,8] ^
+  [v,SvA,vA,Sg;vop3b,8] ^
   })
 
 ; v_addc does not accept an SGPR because the VCC read already counts as an
@@ -1824,7 +1824,7 @@
        (ltu:DI (plus:V_DI 
                  (zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1)))
                  (match_dup 2))
-               (match_dup 1)))]
+               (match_dup 2)))]
   ""
   {@ [cons: =0, 1, 2, =3]
   [v,ASv,v,&Sg] #
@@ -1875,7 +1875,7 @@
          (ltu:DI (plus:V_DI 
                    (zero_extend:V_DI (vec_duplicate:<VnSI> (match_dup 1)))
                    (match_dup 2))
-                 (match_dup 1))
+                 (match_dup 2))
          (match_dup 5)))]
   ""
   {@ [cons: =0, 1, 2, =3, 4, 5]
@@ -1929,7 +1929,7 @@
        (ltu:DI (plus:V_DI 
                  (zero_extend:V_DI (match_dup 1))
                  (vec_duplicate:V_DI (match_dup 2)))
-               (match_dup 1)))]
+               (vec_duplicate:V_DI (match_dup 2))))]
   ""
   {@ [cons: =0, 1, 2, =3]
   [v,v,DbSv,&cV] #
@@ -1978,7 +1978,7 @@
          (ltu:DI (plus:V_DI 
                    (zero_extend:V_DI (match_dup 1))
                    (vec_duplicate:V_DI (match_dup 2)))
-                 (match_dup 1))
+                 (vec_duplicate:V_DI (match_dup 2)))
          (match_dup 5)))]
   ""
   {@ [cons: =0, 1, 2, =3, 4, 5]