I386: Add more testcases for unsigned SAT_ADD vector pattern

Some forms like below failed to be recognized as a SAT_ADD pattern
for target i386.  It is related to some match pattern
extraction but get fixed after the refactor of the SAT_ADD
pattern.  Thus, add testcases to ensure we won't have similar
issues in the future.

  #define DEF_SAT_ADD(T)   \
  T sat_add_##T (T x, T y) \
  {                        \
    T res;                 \
    res = x + y;           \
    res |= -(T)(res < x);  \
    return res;            \
  }

  #define VEC_DEF_SAT_ADD(T)                       \
  void vec_sat_add(T * restrict a, T * restrict b) \
  {                                                \
    for (int i = 0; i < 8; i++)                    \
      b[i] = sat_add_##T (a[i], b[i]);             \
  }

  DEF_SAT_ADD (uint32_t)
  VEC_DEF_SAT_ADD (uint32_t)

The below test suites are passed for this patch.
make -k check-gcc RUNTESTFLAGS="--target_board=unix\{,-m32\} i386.exp=pr112600-5a-*.c"

	PR target/112600

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr112600-5-u16.c: New test.
	* gcc.target/i386/pr112600-5-u32.c: New test.
	* gcc.target/i386/pr112600-5-u64.c: New test.
	* gcc.target/i386/pr112600-5-u8.c: New test.
	* gcc.target/i386/pr112600-5.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/i386/pr112600-5-u16.c b/gcc/testsuite/gcc.target/i386/pr112600-5-u16.c
new file mode 100644 (file)
index 0000000..b058c45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-5-u16.c
@@ -0,0 +1,10 @@
+/* PR target/112600 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
+
+#include "pr112600-5.h"
+
+DEF_SAT_ADD (uint16_t)
+VEC_DEF_SAT_ADD (uint16_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 3 "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr112600-5-u32.c b/gcc/testsuite/gcc.target/i386/pr112600-5-u32.c
new file mode 100644 (file)
index 0000000..04eb990
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-5-u32.c
@@ -0,0 +1,9 @@
+/* PR target/112600 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
+
+#include "pr112600-5.h"
+
+DEF_SAT_ADD (uint32_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr112600-5-u64.c b/gcc/testsuite/gcc.target/i386/pr112600-5-u64.c
new file mode 100644 (file)
index 0000000..55f0f16
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-5-u64.c
@@ -0,0 +1,10 @@
+/* PR target/112600 */
+/* { dg-do compile  { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
+
+#include "pr112600-5.h"
+
+DEF_SAT_ADD (uint64_t)
+
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr112600-5-u8.c b/gcc/testsuite/gcc.target/i386/pr112600-5-u8.c
new file mode 100644 (file)
index 0000000..17fd36a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-5-u8.c
@@ -0,0 +1,10 @@
+/* PR target/112600 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
+
+#include "pr112600-5.h"
+
+DEF_SAT_ADD (uint8_t)
+VEC_DEF_SAT_ADD (uint8_t)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */

diff --git a/gcc/testsuite/gcc.target/i386/pr112600-5.h b/gcc/testsuite/gcc.target/i386/pr112600-5.h
new file mode 100644 (file)
index 0000000..482c865
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr112600-5.h
@@ -0,0 +1,22 @@
+#ifndef HAVE_DEFINED_PR112600_5A_H
+#define HAVE_DEFINED_PR112600_5A_H
+
+#include <stdint.h>
+
+#define DEF_SAT_ADD(T)   \
+T sat_add_##T (T x, T y) \
+{                        \
+  T res;                 \
+  res = x + y;           \
+  res |= -(T)(res < x);  \
+  return res;            \
+}
+
+#define VEC_DEF_SAT_ADD(T)                       \
+void vec_sat_add(T * restrict a, T * restrict b) \
+{                                                \
+  for (int i = 0; i < 16; i++)                   \
+    b[i] = sat_add_##T (a[i], b[i]);             \
+}
+
+#endif