dt-bindings: ti: dpll: add spread spectrum support

DT bindings for enabling and adjusting spread spectrum clocking have
been added.

Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210606202253.31649-3-dariobin@libero.it
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/ti/dpll.txt b/Documentation/devicetree/bindings/clock/ti/dpll.txt
index df57009ff8e74ff48693220908f3a8f1581e15f9..37a7cb6ad07d873fec2b9be8bad19a4ebea7bcc2 100644 (file)
--- a/Documentation/devicetree/bindings/clock/ti/dpll.txt
+++ b/Documentation/devicetree/bindings/clock/ti/dpll.txt
@@ -42,6 +42,11 @@ Required properties:
        "idlest" - contains the idle status register base address
        "mult-div1" - contains the multiplier / divider register base address
        "autoidle" - contains the autoidle register base address (optional)
+       "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
+                      the frequency spreading register base address (optional)
+       "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
+                       the modulation frequency register base address
+                       (optional)
   ti,am3-* dpll types do not have autoidle register
   ti,omap2-* dpll type does not support idlest / autoidle registers
 
@@ -51,6 +56,14 @@ Optional properties:
        - ti,low-power-stop : DPLL supports low power stop mode, gating output
        - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
        - ti,lock : DPLL locks in programmed rate
+       - ti,min-div : the minimum divisor to start from to round the DPLL
+                      target rate
+       - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
+                         spreading in permille (10th of a percent)
+       - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
+                             spectrum modulation frequency
+       - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
+                             to enable the downspread feature
 
 Examples:
        dpll_core_ck: dpll_core_ck@44e00490 {
@@ -83,3 +96,10 @@ Examples:
                clocks = <&sys_ck>, <&sys_ck>;
                reg = <0x0500>, <0x0540>;
        };
+
+       dpll_disp_ck: dpll_disp_ck {
+               #clock-cells = <0>;
+               compatible = "ti,am3-dpll-no-gate-clock";
+               clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+               reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
+       };