[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture

This adds the Tenstorrent Ascalon 8 wide architecture (tt-ascalon-d8)
to the list of known cores.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Add tt-ascalon-d8.
	* config/riscv/riscv.cc (tt_ascalon_d8_tune_info): New.
	* doc/invoke.texi (RISC-V): Add tt-ascalon-d8 to -mcpu.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-tt-ascalon-d8.c: New test.

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 2f5efe3be86a633136899f57765e877eae6dfb12..4fd09e653d26f894184e2273d6945b3c4c82ddf3 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -39,6 +39,7 @@ RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
 RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
 RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
+RISCV_TUNE("tt-ascalon-d8", generic_ooo, tt_ascalon_d8_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
@@ -92,6 +93,13 @@ RISCV_CORE("thead-c906",      "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_"
                              "xtheadmemidx_xtheadmempair_xtheadsync",
                              "thead-c906")
 
+RISCV_CORE("tt-ascalon-d8",   "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_"
+                             "ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_"
+                             "zifencei_zihintntl_zihintpause_zimop_za64rs_"
+                             "zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_"
+                             "zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b",
+                             "tt-ascalon-d8")
+
 RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
                              "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
                              "svinval_zicbom_zicboz",

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ed75c653481f4b573073877d33b82c19299af2fd..4f1f9defc8017226ce9d501127762b0c30910ae3 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -598,6 +598,28 @@ static const struct riscv_tune_param generic_ooo_tune_info = {
   NULL,                                                /* loop_align */
 };
 
+/* Costs to use when optimizing for Tenstorrent Ascalon 8 wide.  */
+static const struct riscv_tune_param tt_ascalon_d8_tune_info = {
+  {COSTS_N_INSNS (2), COSTS_N_INSNS (2)},      /* fp_add */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},      /* fp_mul */
+  {COSTS_N_INSNS (9), COSTS_N_INSNS (16)},     /* fp_div */
+  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)},      /* int_mul */
+  {COSTS_N_INSNS (13), COSTS_N_INSNS (13)},    /* int_div */
+  8,                                           /* issue_rate */
+  3,                                           /* branch_cost */
+  4,                                           /* memory_cost */
+  4,                                           /* fmv_cost */
+  false,                                       /* slow_unaligned_access */
+  true,                                                /* vector_unaligned_access */
+  true,                                                /* use_divmod_expansion */
+  true,                                                /* overlap_op_by_pieces */
+  RISCV_FUSE_NOTHING,                           /* fusible_ops */
+  &generic_vector_cost,                                /* vector cost */
+  NULL,                                                /* function_align */
+  NULL,                                                /* jump_align */
+  NULL,                                                /* loop_align */
+};
+
 /* Costs to use when optimizing for size.  */
 static const struct riscv_tune_param optimize_size_tune_info = {
   {COSTS_N_INSNS (1), COSTS_N_INSNS (1)},      /* fp_add */

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 017bb8075ac56dca43412eba6c309cf8301688c8..749f30e330f42e2be0e7d93fe45571749d375baa 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -30981,7 +30981,8 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21},
 @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76},
 @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76},
 @samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450},
-@samp{sifive-x670}, @samp{thead-c906}, @samp{xiangshan-nanhu}.
+@samp{sifive-x670}, @samp{thead-c906}, @samp{tt-ascalon-d8},
+@samp{xiangshan-nanhu}.
 
 Note that @option{-mcpu} does not override @option{-march} or @option{-mtune}.
 

diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-tt-ascalon-d8.c b/gcc/testsuite/gcc.target/riscv/mcpu-tt-ascalon-d8.c
new file mode 100644 (file)
index 0000000..4c9e13e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-tt-ascalon-d8.c
@@ -0,0 +1,76 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=tt-ascalon-d8 -mabi=lp64d" } */
+/* Tenstorrent tt-ascalon-d8 => rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicond_zicsr_zifencei_zihintntl_zihintpause_zimop_za64rs_zawrs_zfa_zfbfmin_zfh_zcb_zcmop_zba_zbb_zbs_zvbb_zvbc_zvfbfwma_zvfh_zvkng_zvl256b */
+
+#if !((__riscv_xlen == 64)             \
+      && !defined(__riscv_32e)         \
+      && (__riscv_flen == 64)          \
+      && defined(__riscv_i)            \
+      && defined(__riscv_m)            \
+      && defined(__riscv_a)            \
+      && defined(__riscv_f)            \
+      && defined(__riscv_d)            \
+      && defined(__riscv_c)            \
+      && defined(__riscv_b)            \
+      && defined(__riscv_v)            \
+      && defined(__riscv_zic64b)       \
+      && defined(__riscv_zicbom)       \
+      && defined(__riscv_zicbop)       \
+      && defined(__riscv_zicboz)       \
+      && defined(__riscv_ziccamoa)     \
+      && defined(__riscv_ziccif)       \
+      && defined(__riscv_zicclsm)      \
+      && defined(__riscv_ziccrse)      \
+      && defined(__riscv_zicond)       \
+      && defined(__riscv_zicsr)                \
+      && defined(__riscv_zifencei)     \
+      && defined(__riscv_zihintntl)    \
+      && defined(__riscv_zihintpause)  \
+      && defined(__riscv_zimop)                \
+      && defined(__riscv_za64rs)       \
+      && defined(__riscv_zawrs)                \
+      && defined(__riscv_zfa)          \
+      && defined(__riscv_zfbfmin)      \
+      && defined(__riscv_zfh)          \
+      && defined(__riscv_zcb)          \
+      && defined(__riscv_zcmop)                \
+      && defined(__riscv_zba)          \
+      && defined(__riscv_zbb)          \
+      && defined(__riscv_zbs)          \
+      && defined(__riscv_zvbb)         \
+      && defined(__riscv_zvbc)         \
+      && defined(__riscv_zvfbfwma)     \
+      && defined(__riscv_zvfh)         \
+      && defined(__riscv_zvkng)                \
+      && defined(__riscv_zvl256b)      \
+      && defined(__riscv_zmmul)                \
+      && defined(__riscv_zalrsc)       \
+      && defined(__riscv_zaamo)                \
+      && defined(__riscv_zvkb)         \
+      && defined(__riscv_zvkg)         \
+      && defined(__riscv_zvkn)         \
+      && defined(__riscv_zvknc)                \
+      && defined(__riscv_zvkned)       \
+      && defined(__riscv_zvknhb)       \
+      && defined(__riscv_zvkt)         \
+      && defined(__riscv_zca)          \
+      && defined(__riscv_zcd)          \
+      && defined(__riscv_zfhmin)       \
+      && defined(__riscv_zvfbfmin)     \
+      && defined(__riscv_zvl32b)       \
+      && defined(__riscv_zvl64b)       \
+      && defined(__riscv_zvl128b)      \
+      && defined(__riscv_zve32f)       \
+      && defined(__riscv_zve32x)       \
+      && defined(__riscv_zve64f)       \
+      && defined(__riscv_zve64d)       \
+      && defined(__riscv_zve64x)       \
+      )
+#error "unexpected arch"
+#endif
+
+int main()
+{
+  return 0;
+}