6.18-stable patches

added patches:
	x86-cpu-amd-prevent-improper-isolation-of-shared-resources-in-zen2-s-op-cache.patch

diff --git a/queue-6.18/series b/queue-6.18/series
index c2ec1b0bd892dbec2923194c26b1bc0ce7e38b58..645534feeeaa40a309ea7094d466437f792c17f2 100644 (file)
--- a/queue-6.18/series
+++ b/queue-6.18/series
@@ -267,3 +267,4 @@ crypto-caam-guard-hmac-key-hex-dumps-in-hash_digest_key.patch
 net-stmmac-rename-stmmac_get_entry-stmmac_next_entry.patch
 net-stmmac-prevent-null-deref-when-rx-memory-exhausted.patch
 rust-pin-init-fix-incorrect-accessor-reference-lifetime.patch
+x86-cpu-amd-prevent-improper-isolation-of-shared-resources-in-zen2-s-op-cache.patch

diff --git a/queue-6.18/x86-cpu-amd-prevent-improper-isolation-of-shared-resources-in-zen2-s-op-cache.patch b/queue-6.18/x86-cpu-amd-prevent-improper-isolation-of-shared-resources-in-zen2-s-op-cache.patch
new file mode 100644 (file)
index 0000000..e9e7a34
--- /dev/null
+++ b/queue-6.18/x86-cpu-amd-prevent-improper-isolation-of-shared-resources-in-zen2-s-op-cache.patch
@@ -0,0 +1,64 @@
+From c21b90f77687075115d989e53a8ec5e2bb427ab1 Mon Sep 17 00:00:00 2001
+From: Prathyushi Nangia <prathyushi.nangia@amd.com>
+Date: Tue, 9 Dec 2025 10:01:33 -0600
+Subject: x86/CPU/AMD: Prevent improper isolation of shared resources in Zen2's op cache
+
+From: Prathyushi Nangia <prathyushi.nangia@amd.com>
+
+commit c21b90f77687075115d989e53a8ec5e2bb427ab1 upstream.
+
+Make sure resources are not improperly shared in the op cache and
+cause instruction corruption this way.
+
+Signed-off-by: Prathyushi Nangia <prathyushi.nangia@amd.com>
+Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Cc: stable@vger.kernel.org
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/msr-index.h       |    3 ++-
+ arch/x86/kernel/cpu/amd.c              |    3 +++
+ tools/arch/x86/include/asm/msr-index.h |    3 ++-
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -767,9 +767,10 @@
+ #define MSR_AMD64_LBR_SELECT                  0xc000010e
+ 
+ /* Zen4 */
+-#define MSR_ZEN4_BP_CFG                 0xc001102e
++#define MSR_ZEN4_BP_CFG                       0xc001102e
+ #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4
+ #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
++#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT   33
+ 
+ /* Fam 19h MSRs */
+ #define MSR_F19H_UMC_PERF_CTL           0xc0010800
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -994,6 +994,9 @@ static void init_amd_zen2(struct cpuinfo
+ 
+       /* Correct misconfigured CPUID on some clients. */
+       clear_cpu_cap(c, X86_FEATURE_INVLPGB);
++
++      if (!cpu_has(c, X86_FEATURE_HYPERVISOR))
++              msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN2_BP_CFG_BUG_FIX_BIT);
+ }
+ 
+ static void init_amd_zen3(struct cpuinfo_x86 *c)
+--- a/tools/arch/x86/include/asm/msr-index.h
++++ b/tools/arch/x86/include/asm/msr-index.h
+@@ -761,9 +761,10 @@
+ #define MSR_AMD64_LBR_SELECT                  0xc000010e
+ 
+ /* Zen4 */
+-#define MSR_ZEN4_BP_CFG                 0xc001102e
++#define MSR_ZEN4_BP_CFG                       0xc001102e
+ #define MSR_ZEN4_BP_CFG_BP_SPEC_REDUCE_BIT 4
+ #define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
++#define MSR_ZEN2_BP_CFG_BUG_FIX_BIT   33
+ 
+ /* Fam 19h MSRs */
+ #define MSR_F19H_UMC_PERF_CTL           0xc0010800