iommu/mediatek: Setting MISC_CTRL register

Add F_MMU_IN_ORDER_WR_EN_MASK and F_MMU_STANDARD_AXI_MODE_EN_MASK
definitions in MISC_CTRL register.
F_MMU_STANDARD_AXI_MODE_EN_MASK:
If we set F_MMU_STANDARD_AXI_MODE_EN_MASK (bit[3][19] = 0, not follow
standard AXI protocol), the iommu will priorize sending of urgent read
command over a normal read command. This improves the performance.
F_MMU_IN_ORDER_WR_EN_MASK:
If we set F_MMU_IN_ORDER_WR_EN_MASK (bit[1][17] = 0, out-of-order write),
the iommu will re-order write commands and send the write commands with
higher priority. Otherwise the sending of write commands will be done in
order. The feature is controlled by OUT_ORDER_WR_EN platform data flag.

Suggested-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20200703044127.27438-5-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 40ca564d97af34c49a97690a5b3d0e2d7d40728b..219d7aa6f059c35f7ec684afb38857d8f673fe11 100644 (file)
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -42,6 +42,9 @@
 #define F_INVLD_EN1                            BIT(1)
 
 #define REG_MMU_MISC_CTRL                      0x048
+#define F_MMU_IN_ORDER_WR_EN_MASK              (BIT(1) | BIT(17))
+#define F_MMU_STANDARD_AXI_MODE_MASK           (BIT(3) | BIT(19))
+
 #define REG_MMU_DCM_DIS                                0x050
 
 #define REG_MMU_CTRL_REG                       0x110
@@ -105,6 +108,7 @@
 #define HAS_BCLK                       BIT(1)
 #define HAS_VLD_PA_RNG                 BIT(2)
 #define RESET_AXI                      BIT(3)
+#define OUT_ORDER_WR_EN                        BIT(4)
 
 #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
                ((((pdata)->flags) & (_x)) == (_x))
@@ -585,8 +589,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
 
        if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) {
                /* The register is called STANDARD_AXI_MODE in this case */
-               writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
+               regval = 0;
+       } else {
+               regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
+               regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+               if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
+                       regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
        }
+       writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
 
        if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
                             dev_name(data->dev), (void *)data)) {