drm/amd/display: Add DCN36 CORE

Add DCN36 support in dc_resource.c.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Martin Leung <martin.leung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index f59722e17abde27eeb8f9f5e3b617dd5ca3e7f2a..bf14fa1e3771f38a5f8facc53845336b7629dce8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -76,6 +76,7 @@
 #include "dcn321/dcn321_resource.h"
 #include "dcn35/dcn35_resource.h"
 #include "dcn351/dcn351_resource.h"
+#include "dcn36/dcn36_resource.h"
 #include "dcn401/dcn401_resource.h"
 #if defined(CONFIG_DRM_AMD_DC_FP)
 #include "dc_spl_translate.h"
@@ -204,6 +205,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
                dc_version = DCN_VERSION_3_5;
                if (ASICREV_IS_GC_11_0_4(asic_id.hw_internal_rev))
                        dc_version = DCN_VERSION_3_51;
+               if (ASICREV_IS_DCN36(asic_id.hw_internal_rev))
+                       dc_version = DCN_VERSION_3_6;
                break;
        case AMDGPU_FAMILY_GC_12_0_0:
                if (ASICREV_IS_GC_12_0_1_A0(asic_id.hw_internal_rev) ||
@@ -320,6 +323,9 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        case DCN_VERSION_3_51:
                res_pool = dcn351_create_resource_pool(init_data, dc);
                break;
+       case DCN_VERSION_3_6:
+               res_pool = dcn36_create_resource_pool(init_data, dc);
+               break;
        case DCN_VERSION_4_01:
                res_pool = dcn401_create_resource_pool(init_data, dc);
                break;