--- /dev/null
+#objdump: -dw
+#name: AVX512 instructions do not need {evex} prefix with memory
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 f1 7d 08 71 14 88 1f\s+vpsrlw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 71 24 88 1f\s+vpsraw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 71 34 88 1f\s+vpsllw\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 72 24 88 1f\s+vpsrad\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 fd 08 72 24 88 1f\s+vpsraq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 fd 08 72 e1 1f\s+vpsraq\s+\$0x1f,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f1 f5 08 e2 04 88\s+vpsraq\s+\(%eax,%ecx,4\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f1 f5 08 e2 c2\s+vpsraq\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 73 1c 88 1f\s+vpsrldq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 73 3c 88 1f\s+vpslldq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 72 14 88 1f\s+vpsrld\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 7d 08 72 34 88 1f\s+vpslld\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 fd 08 73 14 88 1f\s+vpsrlq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 fd 08 73 34 88 1f\s+vpsllq\s+\$0x1f,\(%eax,%ecx,4\),%xmm0
+#pass
--- /dev/null
+# Check instructions do not need {evex} prefix under memory operand
+
+ .text
+_start:
+ vpsrlw $0x1f,(%eax,%ecx,4),%xmm0
+ vpsraw $0x1f,(%eax,%ecx,4),%xmm0
+ vpsllw $0x1f,(%eax,%ecx,4),%xmm0
+ vpsrad $0x1f,(%eax,%ecx,4),%xmm0
+ vpsraq $0x1f,(%eax,%ecx,4),%xmm0
+ vpsraq $0x1f,%xmm1,%xmm0
+ vpsraq (%eax,%ecx,4),%xmm1,%xmm0
+ vpsraq %xmm2,%xmm1,%xmm0
+ vpsrldq $0x1f,(%eax,%ecx,4),%xmm0
+ vpslldq $0x1f,(%eax,%ecx,4),%xmm0
+ vpsrld $0x1f,(%eax,%ecx,4),%xmm0
+ vpslld $0x1f,(%eax,%ecx,4),%xmm0
+ vpsrlq $0x1f,(%eax,%ecx,4),%xmm0
+ vpsllq $0x1f,(%eax,%ecx,4),%xmm0
run_dump_test "evex-lig-2"
run_dump_test "evex-wig1"
run_dump_test "evex-wig1-intel"
+ run_dump_test "evex-only"
run_dump_test "evex-no-scale-32"
run_dump_test "sse2avx"
run_dump_test "unaligned-vector-move"
--- /dev/null
+#objdump: -dw
+#name: x86-64 AVX512 instructions do not need {evex} prefix with memory
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*62 d1 7d 08 71 14 8f 1f\s+vpsrlw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 71 24 8f 1f\s+vpsraw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 71 34 8f 1f\s+vpsllw\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 72 24 8f 1f\s+vpsrad\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 fd 08 72 24 8f 1f\s+vpsraq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 f1 fd 08 72 e1 1f\s+vpsraq\s+\$0x1f,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d1 f5 08 e2 04 8f\s+vpsraq\s+\(%r15,%rcx,4\),%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 f1 f5 08 e2 c2\s+vpsraq\s+%xmm2,%xmm1,%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 73 1c 8f 1f\s+vpsrldq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 73 3c 8f 1f\s+vpslldq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 72 14 8f 1f\s+vpsrld\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 7d 08 72 34 8f 1f\s+vpslld\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 fd 08 73 14 8f 1f\s+vpsrlq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+\s*[a-f0-9]+:\s*62 d1 fd 08 73 34 8f 1f\s+vpsllq\s+\$0x1f,\(%r15,%rcx,4\),%xmm0
+#pass
--- /dev/null
+# Check instructions do not need {evex} prefix under memory operand
+
+ .text
+_start:
+ vpsrlw $0x1f,(%r15,%rcx,4),%xmm0
+ vpsraw $0x1f,(%r15,%rcx,4),%xmm0
+ vpsllw $0x1f,(%r15,%rcx,4),%xmm0
+ vpsrad $0x1f,(%r15,%rcx,4),%xmm0
+ vpsraq $0x1f,(%r15,%rcx,4),%xmm0
+ vpsraq $0x1f,%xmm1,%xmm0
+ vpsraq (%r15,%rcx,4),%xmm1,%xmm0
+ vpsraq %xmm2,%xmm1,%xmm0
+ vpsrldq $0x1f,(%r15,%rcx,4),%xmm0
+ vpslldq $0x1f,(%r15,%rcx,4),%xmm0
+ vpsrld $0x1f,(%r15,%rcx,4),%xmm0
+ vpslld $0x1f,(%r15,%rcx,4),%xmm0
+ vpsrlq $0x1f,(%r15,%rcx,4),%xmm0
+ vpsllq $0x1f,(%r15,%rcx,4),%xmm0
run_dump_test "x86-64-evex-wig1"
run_dump_test "x86-64-evex-wig1-intel"
run_dump_test "x86-64-evex-wig2"
+run_dump_test "x86-64-evex-only"
run_dump_test "evex-no-scale-64"
run_dump_test "x86-64-sse2avx"
run_dump_test "x86-64-unaligned-vector-move"
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "%XEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "%XEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "%XEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* REG_EVEX_0F72 */
{
{ "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
{ VEX_W_TABLE (EVEX_W_0F72_R_2) },
{ Bad_Opcode },
- { "%XEvpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
+ { VEX_W_TABLE (EVEX_W_0F72_R_4) },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F72_R_6) },
},
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F73_R_2) },
- { "%XEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsrldqY", { Vex, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F73_R_6) },
- { "%XEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpslldqY", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* REG_EVEX_0F38C6_L_2 */
{
},
/* EVEX_W_0F72_R_2 */
{
- { "%XEvpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
+ },
+ /* EVEX_W_0F72_R_4 */
+ {
+ { "%MEvpsrad", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "vpsraq", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F72_R_6 */
{
- { "%XEvpslld", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpslld", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F73_R_2 */
{
{ Bad_Opcode },
- { "%XEvpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F73_R_6 */
{
{ Bad_Opcode },
- { "%XEvpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
+ { "%MEvpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
},
/* EVEX_W_0F76 */
{
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0FD6) },
},
+ /* EVEX_W_0FE2 */
+ {
+ { "%XEvpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpsraq", { XM, Vex, EXxmm }, PREFIX_DATA },
+ },
/* EVEX_W_0FE6_P_1 */
{
{ "%XEvcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
/* E0 */
{ "%XEvpavgb", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
- { "%XEvpsra%DQ", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { VEX_W_TABLE (EVEX_W_0FE2) },
{ "%XEvpavgw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
{ "%XEvpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
EVEX_W_0F6F_P_3,
EVEX_W_0F70_P_2,
EVEX_W_0F72_R_2,
+ EVEX_W_0F72_R_4,
EVEX_W_0F72_R_6,
EVEX_W_0F73_R_2,
EVEX_W_0F73_R_6,
EVEX_W_0FD3,
EVEX_W_0FD4,
EVEX_W_0FD6,
+ EVEX_W_0FE2,
EVEX_W_0FE6_P_1,
EVEX_W_0FE7,
EVEX_W_0FF2,
"XV" => print "{vex} " pseudo prefix
"XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
is used by an EVEX-encoded (AVX512VL) instruction.
+ "ME" => Similar to "XE", but only print "{evex} " when there is no
+ memory operand.
"NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
pseudo prefix when instructions without NF, EGPR and VVVV,
"NE" => don't print "{evex} " pseudo prefix for some special instructions
{
switch (last[0])
{
+ case 'M':
+ if (ins->modrm.mod != 3)
+ break;
+ /* Fall through. */
case 'X':
if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
|| (ins->rex2 & 7)