+2012-07-30 Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * common/config/i386/i386-common.c (OPTION_MASK_ISA_RDSEED_SET): New.
+ (OPTION_MASK_ISA_RDSEED_UNSET): Likewise.
+ (ix86_handle_option): Handle mrdseed option.
+ * config.gcc (i[34567]86-*-*): Add rdseedintrin.h.
+ (x86_64-*-*): Likewise.
+ * config/i386/prfchwintrin.h: New header.
+ * config/i386/cpuid.h (bit_RDSEED): New.
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect
+ RDSEED support.
+ * config/i386/i386-c.c: Define __RDSEED__ if needed.
+ * config/i386/i386.c (ix86_target_string): Define
+ -mrdseed option.
+ (PTA_RDSEED): New.
+ (ix86_option_override_internal): Handle new option.
+ (ix86_valid_target_attribute_inner_p): Add OPT_mrdseed.
+ (ix86_builtins): Add enum entries for RDSEED* builtins.
+ (ix86_init_mmx_sse_builtins): Define new builtins.
+ (ix86_expand_builtin): Expand RDSEED* builtins.
+ * config/i386/i386.h (TARGET_RDSEED): New.
+ * config/i386/i386.md (rdseed<mode>_1): New.
+ * config/i386/i386.opt (mrdseed): New.
+ * config/i386/x86intrin.h: Include rdseedintrin.h.
+
2012-07-30 Richard Guenther <rguenther@suse.de>
* tree-into-ssa.c (mark_def_sites): Also process virtual operands.
(OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
#define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
+#define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
#define OPTION_MASK_ISA_AVX2_UNSET OPTION_MASK_ISA_AVX2
#define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
#define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
+#define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
}
return true;
+ case OPT_mrdseed:
+ if (value)
+ {
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
+ }
+ return true;
+
case OPT_mprfchw:
if (value)
{
ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
lzcntintrin.h bmiintrin.h bmi2intrin.h tbmintrin.h
avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
- xtestintrin.h prfchwintrin.h"
+ xtestintrin.h rdseedintrin.h prfchwintrin.h"
;;
x86_64-*-*)
cpu_type=i386
ia32intrin.h cross-stdarg.h lwpintrin.h popcntintrin.h
lzcntintrin.h bmiintrin.h tbmintrin.h bmi2intrin.h
avx2intrin.h fmaintrin.h f16cintrin.h rtmintrin.h
- xtestintrin.h prfchwintrin.h"
+ xtestintrin.h rdseedintrin.h prfchwintrin.h"
need_64bit_hwint=yes
;;
ia64-*-*)
unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
unsigned int has_hle = 0, has_rtm = 0;
unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
- unsigned int has_prfchw = 0;
+ unsigned int has_rdseed = 0, has_prfchw = 0;
bool arch;
has_avx2 = ebx & bit_AVX2;
has_bmi2 = ebx & bit_BMI2;
has_fsgsbase = ebx & bit_FSGSBASE;
+ has_rdseed = ebx & bit_RDSEED;
has_prfchw = ecx & bit_PRFCHW;
}
const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
+ const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
options = concat (options, cx16, sahf, movbe, ase, pclmul,
popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
- hle, rdrnd, f16c, fsgsbase, prfchw, NULL);
+ hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, NULL);
}
done:
def_or_undef (parse_in, "__RDRND__");
if (isa_flag & OPTION_MASK_ISA_F16C)
def_or_undef (parse_in, "__F16C__");
+ if (isa_flag & OPTION_MASK_ISA_RDSEED)
+ def_or_undef (parse_in, "__RDSEED__");
if (isa_flag & OPTION_MASK_ISA_PRFCHW)
def_or_undef (parse_in, "__PRFCHW__");
if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
{ "-mbmi2", OPTION_MASK_ISA_BMI2 },
{ "-mlzcnt", OPTION_MASK_ISA_LZCNT },
{ "-mhle", OPTION_MASK_ISA_HLE },
+ { "-mrdseed", OPTION_MASK_ISA_RDSEED },
{ "-mprfchw", OPTION_MASK_ISA_PRFCHW },
{ "-mtbm", OPTION_MASK_ISA_TBM },
{ "-mpopcnt", OPTION_MASK_ISA_POPCNT },
#define PTA_RTM (HOST_WIDE_INT_1 << 32)
#define PTA_HLE (HOST_WIDE_INT_1 << 33)
#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
+#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
/* if this reaches 64, need to widen struct pta flags below */
static struct pta
if (processor_alias_table[i].flags & PTA_PRFCHW
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
+ if (processor_alias_table[i].flags & PTA_RDSEED
+ && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
+ ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
IX86_ATTR_ISA ("rtm", OPT_mrtm),
IX86_ATTR_ISA ("hle", OPT_mhle),
IX86_ATTR_ISA ("prfchw", OPT_mprfchw),
+ IX86_ATTR_ISA ("rdseed", OPT_mrdseed),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
IX86_BUILTIN_RDRAND32_STEP,
IX86_BUILTIN_RDRAND64_STEP,
+ /* RDSEED instructions. */
+ IX86_BUILTIN_RDSEED16_STEP,
+ IX86_BUILTIN_RDSEED32_STEP,
+ IX86_BUILTIN_RDSEED64_STEP,
+
/* F16C instructions. */
IX86_BUILTIN_CVTPH2PS,
IX86_BUILTIN_CVTPH2PS256,
def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi",
V16QI_FTYPE_V16QI_QI_INT, IX86_BUILTIN_VEC_SET_V16QI);
+ /* RDSEED */
+ def_builtin (OPTION_MASK_ISA_RDSEED, "__builtin_ia32_rdseed_hi_step",
+ INT_FTYPE_PUSHORT, IX86_BUILTIN_RDSEED16_STEP);
+ def_builtin (OPTION_MASK_ISA_RDSEED, "__builtin_ia32_rdseed_si_step",
+ INT_FTYPE_PUNSIGNED, IX86_BUILTIN_RDSEED32_STEP);
+ def_builtin (OPTION_MASK_ISA_RDSEED && OPTION_MASK_ISA_64BIT,
+ "__builtin_ia32_rdseed_di_step",
+ INT_FTYPE_PULONGLONG, IX86_BUILTIN_RDSEED64_STEP);
+
/* Add FMA4 multi-arg argument instructions */
for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
{
gen_rtx_IF_THEN_ELSE (SImode, pat, op2, op1)));
return target;
+ case IX86_BUILTIN_RDSEED16_STEP:
+ icode = CODE_FOR_rdseedhi_1;
+ mode0 = HImode;
+ goto rdseed_step;
+
+ case IX86_BUILTIN_RDSEED32_STEP:
+ icode = CODE_FOR_rdseedsi_1;
+ mode0 = SImode;
+ goto rdseed_step;
+
+ case IX86_BUILTIN_RDSEED64_STEP:
+ icode = CODE_FOR_rdseeddi_1;
+ mode0 = DImode;
+
+rdseed_step:
+ op0 = gen_reg_rtx (mode0);
+ emit_insn (GEN_FCN (icode) (op0));
+
+ arg0 = CALL_EXPR_ARG (exp, 0);
+ op1 = expand_normal (arg0);
+ if (!address_operand (op1, VOIDmode))
+ {
+ op1 = convert_memory_address (Pmode, op1);
+ op1 = copy_addr_to_reg (op1);
+ }
+ emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
+
+ op2 = gen_reg_rtx (QImode);
+
+ pat = gen_rtx_LTU (QImode, gen_rtx_REG (CCCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, op2, pat));
+
+ if (target == 0)
+ target = gen_reg_rtx (SImode);
+
+ emit_insn (gen_zero_extendqisi2 (target, op2));
+
+ return target;
+
case IX86_BUILTIN_GATHERSIV2DF:
icode = CODE_FOR_avx2_gathersiv2df;
goto gather_gen;
#define TARGET_F16C OPTION_ISA_F16C
#define TARGET_RTM OPTION_ISA_RTM
#define TARGET_HLE OPTION_ISA_HLE
+#define TARGET_RDSEED OPTION_ISA_RDSEED
#define TARGET_PRFCHW OPTION_ISA_PRFCHW
#define TARGET_LP64 OPTION_ABI_64
;; For RDRAND support
UNSPECV_RDRAND
+ ;; For RDSEED support
+ UNSPECV_RDSEED
+
;; For RTM support
UNSPECV_XBEGIN
UNSPECV_XEND
[(set_attr "type" "other")
(set_attr "prefix_extra" "1")])
+(define_insn "rdseed<mode>_1"
+ [(set (match_operand:SWI248 0 "register_operand" "=r")
+ (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDSEED))
+ (set (reg:CCC FLAGS_REG)
+ (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDSEED))]
+ "TARGET_RDSEED"
+ "rdseed\t%0"
+ [(set_attr "type" "other")
+ (set_attr "prefix_extra" "1")])
+
(define_expand "pause"
[(set (match_dup 0)
(unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))]
Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save
Support Hardware Lock Elision prefixes
+mrdseed
+Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save
+Support RDSEED instruction
+
mprfchw
Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save
Support PREFETCHW instruction
--- /dev/null
+/* Copyright (C) 2012 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _X86INTRIN_H_INCLUDED
+# error "Never use <rdseedintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef __RDSEED__
+# error "RDSEED instruction not enabled"
+#endif /* __RDSEED__ */
+
+#ifndef _RDSEEDINTRIN_H_INCLUDED
+#define _RDSEEDINTRIN_H_INCLUDED
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdseed16_step (unsigned short *p)
+{
+ return __builtin_ia32_rdseed_hi_step (p);
+}
+
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdseed32_step (unsigned int *p)
+{
+ return __builtin_ia32_rdseed_si_step (p);
+}
+
+#ifdef __x86_64__
+extern __inline int
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_rdseed64_step (unsigned long long *p)
+{
+ return __builtin_ia32_rdseed_di_step (p);
+}
+#endif
+
+#endif /* _RDSEEDINTRIN_H_INCLUDED */
#include <popcntintrin.h>
#endif
+#ifdef __RDSEED__
+#include <rdseedintrin.h>
+#endif
+
#ifdef __PRFCHW__
#include <prfchwintrin.h>
#endif
+2012-07-30 Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * gcc.target/i386/rdseed16-1.c: New.
+ * gcc.target/i386/rdseed32-1.c: Ditto
+ * gcc.target/i386/rdseed64-1.c: Ditto
+ * gcc.target/i386/sse-12.c: Add -mrdseed.
+ * gcc.target/i386/sse-13.c: Ditto.
+ * gcc.target/i386/sse-14.c: Ditto.
+ * g++.dg/other/i386-2.C: Ditto.
+ * g++.dg/other/i386-3.C: Ditto.
+
2012-07-30 Oleg Endo <olegendo@gcc.gnu.org>
PR target/51244
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned short *p)
+{
+ volatile int r;
+ r = _rdseed16_step (p);
+}
+
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned int *p)
+{
+ volatile int r;
+ r = _rdseed32_step (p);
+}
+
--- /dev/null
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mrdseed -O2" } */
+/* { dg-final { scan-assembler "rdseed\[ \\t\]+" } } */
+
+#include <x86intrin.h>
+
+void extern
+rdseed_test (unsigned long long *p)
+{
+ volatile int r;
+ r = _rdseed64_step (p);
+}
+
popcntintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */
#include <x86intrin.h>
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */
#include <mm_malloc.h>
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mprfchw" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw" } */
#include <mm_malloc.h>
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,prfchw")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw")
#endif
/* Following intrinsics require immediate arguments. They
/* x86intrin.h (FMA4/XOP/LWP/BMI/BMI2/TBM/LZCNT/FMA). */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,prfchw")
+#pragma GCC target ("fma4,xop,lwp,bmi,bmi2,tbm,lzcnt,fma,rdseed,prfchw")
#endif
#include <x86intrin.h>
/* xopintrin.h */
/* rtmintrin.h */
#define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1)
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,prfchw")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw")
#include <wmmintrin.h>
#include <smmintrin.h>
#include <mm3dnow.h>