cxl: Calculate and store PCI link latency for the downstream ports

The latency is calculated by dividing the flit size over the bandwidth. Add
support to retrieve the flit size for the CXL switch device and calculate
the latency of the PCIe link. Cache the latency number with cxl_dport.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/170319621931.2212653.6800240203604822886.stgit@djiang5-mobl3
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 86d7ba23235e3bdefb567e3dc3cb656b4f9593c0..3b64fb1b9ed058055fa80220fc2b83b109cc6e17 100644 (file)
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -88,4 +88,6 @@ enum cxl_poison_trace_type {
        CXL_POISON_TRACE_CLEAR,
 };
 
+long cxl_pci_get_latency(struct pci_dev *pdev);
+
 #endif /* __CXL_CORE_H__ */

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 37e1652afbc7eac56fffbb0a5692ea2a1cd82411..6c9c8d92f8f71401af70fec26be60e0339c18c64 100644 (file)
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright(c) 2021 Intel Corporation. All rights reserved. */
+#include <linux/units.h>
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <linux/device.h>
 #include <linux/delay.h>
@@ -979,3 +980,38 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
        return PCI_ERS_RESULT_NEED_RESET;
 }
 EXPORT_SYMBOL_NS_GPL(cxl_error_detected, CXL);
+
+static int cxl_flit_size(struct pci_dev *pdev)
+{
+       if (cxl_pci_flit_256(pdev))
+               return 256;
+
+       return 68;
+}
+
+/**
+ * cxl_pci_get_latency - calculate the link latency for the PCIe link
+ * @pdev: PCI device
+ *
+ * return: calculated latency or 0 for no latency
+ *
+ * CXL Memory Device SW Guide v1.0 2.11.4 Link latency calculation
+ * Link latency = LinkPropagationLatency + FlitLatency + RetimerLatency
+ * LinkProgationLatency is negligible, so 0 will be used
+ * RetimerLatency is assumed to be negligible and 0 will be used
+ * FlitLatency = FlitSize / LinkBandwidth
+ * FlitSize is defined by spec. CXL rev3.0 4.2.1.
+ * 68B flit is used up to 32GT/s. >32GT/s, 256B flit size is used.
+ * The FlitLatency is converted to picoseconds.
+ */
+long cxl_pci_get_latency(struct pci_dev *pdev)
+{
+       long bw;
+
+       bw = pcie_link_speed_mbps(pdev);
+       if (bw < 0)
+               return 0;
+       bw /= BITS_PER_BYTE;
+
+       return cxl_flit_size(pdev) * MEGA / bw;
+}

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 9393cbf0465287f7370e62015bcfe4c195c3080c..b5ad227fe0d8f82f2da401f503c27c7f89f9df8a 100644 (file)
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -854,6 +854,9 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host,
        if (rc)
                return ERR_PTR(rc);
 
+       if (parent_dport && dev_is_pci(uport_dev))
+               port->pci_latency = cxl_pci_get_latency(to_pci_dev(uport_dev));
+
        return port;
 
 err:
@@ -1137,6 +1140,9 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
        if (rc)
                return ERR_PTR(rc);
 
+       if (dev_is_pci(dport_dev))
+               dport->link_latency = cxl_pci_get_latency(to_pci_dev(dport_dev));
+
        return dport;
 }
 

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index abbdcd3a75961413ea17262cc9ec0c3d7b57126a..7da8db919a20dcec42acc3e4a1608e1a8f1ff533 100644 (file)
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -591,6 +591,7 @@ struct cxl_dax_region {
  * @depth: How deep this port is relative to the root. depth 0 is the root.
  * @cdat: Cached CDAT data
  * @cdat_available: Should a CDAT attribute be available in sysfs
+ * @pci_latency: Upstream latency in picoseconds
  */
 struct cxl_port {
        struct device dev;
@@ -613,6 +614,7 @@ struct cxl_port {
                size_t length;
        } cdat;
        bool cdat_available;
+       long pci_latency;
 };
 
 struct cxl_root_ops {
@@ -659,6 +661,7 @@ struct cxl_rcrb_info {
  * @port: reference to cxl_port that contains this downstream port
  * @regs: Dport parsed register blocks
  * @sw_coord: access coordinates (performance) for switch from CDAT
+ * @link_latency: calculated PCIe downstream latency
  */
 struct cxl_dport {
        struct device *dport_dev;
@@ -669,6 +672,7 @@ struct cxl_dport {
        struct cxl_port *port;
        struct cxl_regs regs;
        struct access_coordinate sw_coord;
+       long link_latency;
 };
 
 /**

diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 0fa4799ea316cd802c97feda11fb6e3c88aaa138..711b05d9a370e91b49beffbc5494542d8861d31e 100644 (file)
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -85,6 +85,19 @@ struct cdat_entry_header {
        __le16 length;
 } __packed;
 
+/*
+ * CXL v3.0 6.2.3 Table 6-4
+ * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
+ * mode, otherwise it's 68B flits mode.
+ */
+static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
+{
+       u16 lnksta2;
+
+       pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2);
+       return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
+}
+
 int devm_cxl_port_enumerate_dports(struct cxl_port *port);
 struct cxl_dev_state;
 int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm,

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 55bc3576a98562807522e233223119f047822056..00817d403ad4e110b955100f821188ea91ad31c3 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -6224,6 +6224,41 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
 }
 EXPORT_SYMBOL(pcie_set_mps);
 
+static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
+{
+       return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
+}
+
+int pcie_link_speed_mbps(struct pci_dev *pdev)
+{
+       u16 lnksta;
+       int err;
+
+       err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
+       if (err)
+               return err;
+
+       switch (to_pcie_link_speed(lnksta)) {
+       case PCIE_SPEED_2_5GT:
+               return 2500;
+       case PCIE_SPEED_5_0GT:
+               return 5000;
+       case PCIE_SPEED_8_0GT:
+               return 8000;
+       case PCIE_SPEED_16_0GT:
+               return 16000;
+       case PCIE_SPEED_32_0GT:
+               return 32000;
+       case PCIE_SPEED_64_0GT:
+               return 64000;
+       default:
+               break;
+       }
+
+       return -EINVAL;
+}
+EXPORT_SYMBOL(pcie_link_speed_mbps);
+
 /**
  * pcie_bandwidth_available - determine minimum link settings of a PCIe
  *                           device and its bandwidth limitation
@@ -6257,8 +6292,7 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
        while (dev) {
                pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
 
-               next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS,
-                                                      lnksta)];
+               next_speed = to_pcie_link_speed(lnksta);
                next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
 
                next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);

diff --git a/include/linux/pci.h b/include/linux/pci.h
index dea043bc1e383acc4c18e83d506d1ffe5c489448..504a4ba2c29efd6c79e0590edaf6260bbb8c22b5 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1364,6 +1364,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps);
 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
                             enum pci_bus_speed *speed,
                             enum pcie_link_width *width);
+int pcie_link_speed_mbps(struct pci_dev *pdev);
 void pcie_print_link_status(struct pci_dev *dev);
 int pcie_reset_flr(struct pci_dev *dev, bool probe);
 int pcie_flr(struct pci_dev *dev);