When simplifying (improving) the IR generated by the ARM front end, do

CSE by default.  This significantly improves performance for ARM (not
Thumb) code that leans heavily on predicated instructions by commoning
up duplicate condition code evaluations within a single IRSB.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2137

diff --git a/VEX/priv/ir_opt.c b/VEX/priv/ir_opt.c
index 504105b1f45a78b9a446e9d1ffebdf535d499218..5cf91dc456303a91a733980291c7899342b00396 100644 (file)
--- a/VEX/priv/ir_opt.c
+++ b/VEX/priv/ir_opt.c
@@ -4714,6 +4714,7 @@ IRSB* do_iropt_BB(
       bb = cprop_BB(bb);
       bb = spec_helpers_BB ( bb, specHelper );
       redundant_put_removal_BB ( bb, preciseMemExnsFn );
+      do_cse_BB( bb );
       do_deadcode_BB( bb );
    }