Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable good.
However, I saw GCN also has 1024 bit vector.
This patch may cause this case FAIL in GCN port ?
Hi, GCN folk, could you check this patch in GCN port for me ?
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr65935.c: Add vect1024 variant.
* lib/target-supports.exp: Ditto.
/* We should also be able to use 2-lane SLP to initialize the real and
imaginary components in the first loop of main. */
-/* { dg-final { scan-tree-dump-times "optimized: basic block" 10 "slp1" } } */
+/* { dg-final { scan-tree-dump-times "optimized: basic block" 10 "slp1" { target {! { vect1024 } } } } } */
+/* { dg-final { scan-tree-dump-times "optimized: basic block" 11 "slp1" { target { { vect1024 } } } } } */
/* We should see the s->phase[dir] operand splatted and no other operand built
from scalars. See PR97334. */
/* { dg-final { scan-tree-dump "Using a splat" "slp1" } } */
return [expr { [lindex [available_vector_sizes] 0] == 0 }]
}
+# Return 1 if the target supports vectors of 1024 bits.
+
+proc check_effective_target_vect1024 { } {
+ return [expr { [lsearch -exact [available_vector_sizes] 1024] >= 0 }]
+}
+
# Return 1 if the target supports vectors of 512 bits.
proc check_effective_target_vect512 { } {