--- /dev/null
+From 0d08e7bf0d0d1a29aff7b16ef516f7415eb1aa05 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= <mirq-linux@rere.qmqm.pl>
+Date: Thu, 4 Nov 2021 17:28:28 +0100
+Subject: ARM: 9155/1: fix early early_iounmap()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Michał Mirosław <mirq-linux@rere.qmqm.pl>
+
+commit 0d08e7bf0d0d1a29aff7b16ef516f7415eb1aa05 upstream.
+
+Currently __set_fixmap() bails out with a warning when called in early boot
+from early_iounmap(). Fix it, and while at it, make the comment a bit easier
+to understand.
+
+Cc: <stable@vger.kernel.org>
+Fixes: b089c31c519c ("ARM: 8667/3: Fix memory attribute inconsistencies when using fixmap")
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/mm/mmu.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -391,9 +391,9 @@ void __set_fixmap(enum fixed_addresses i
+ FIXADDR_END);
+ BUG_ON(idx >= __end_of_fixed_addresses);
+
+- /* we only support device mappings until pgprot_kernel has been set */
++ /* We support only device mappings before pgprot_kernel is set. */
+ if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
+- pgprot_val(pgprot_kernel) == 0))
++ pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
+ return;
+
+ if (pgprot_val(prot))
--- /dev/null
+From 418ace9992a7647c446ed3186df40cf165b67298 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Sat, 6 Nov 2021 19:42:29 +0100
+Subject: ARM: 9156/1: drop cc-option fallbacks for architecture selection
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit 418ace9992a7647c446ed3186df40cf165b67298 upstream.
+
+Naresh and Antonio ran into a build failure with latest Debian
+armhf compilers, with lots of output like
+
+ tmp/ccY3nOAs.s:2215: Error: selected processor does not support `cpsid i' in ARM mode
+
+As it turns out, $(cc-option) fails early here when the FPU is not
+selected before CPU architecture is selected, as the compiler
+option check runs before enabling -msoft-float, which causes
+a problem when testing a target architecture level without an FPU:
+
+cc1: error: '-mfloat-abi=hard': selected architecture lacks an FPU
+
+Passing e.g. -march=armv6k+fp in place of -march=armv6k would avoid this
+issue, but the fallback logic is already broken because all supported
+compilers (gcc-5 and higher) are much more recent than these options,
+and building with -march=armv5t as a fallback no longer works.
+
+The best way forward that I see is to just remove all the checks, which
+also has the nice side-effect of slightly improving the startup time for
+'make'.
+
+The -mtune=marvell-f option was apparently never supported by any mainline
+compiler, and the custom Codesourcery gcc build that did support is
+now too old to build kernels, so just use -mtune=xscale unconditionally
+for those.
+
+This should be safe to apply on all stable kernels, and will be required
+in order to keep building them with gcc-11 and higher.
+
+Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=996419
+
+Reported-by: Antonio Terceiro <antonio.terceiro@linaro.org>
+Reported-by: Naresh Kamboju <naresh.kamboju@linaro.org>
+Reported-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc>
+Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Tested-by: Klaus Kudielka <klaus.kudielka@gmail.com>
+Cc: Matthias Klose <doko@debian.org>
+Cc: stable@vger.kernel.org
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm/Makefile | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+--- a/arch/arm/Makefile
++++ b/arch/arm/Makefile
+@@ -60,15 +60,15 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i
+ # Note that GCC does not numerically define an architecture version
+ # macro, but instead defines a whole series of macros which makes
+ # testing for a specific architecture or later rather impossible.
+-arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
+-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+-arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
++arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m
++arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a
++arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6
+ # Only override the compiler option if ARMv6. The ARMv6K extensions are
+ # always available in ARMv7
+ ifeq ($(CONFIG_CPU_32v6),y)
+-arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
++arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k
+ endif
+-arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
++arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te
+ arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t
+ arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4
+ arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m
+@@ -82,7 +82,7 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7t
+ tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi
+ tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi
+ tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi
+-tune-$(CONFIG_CPU_ARM946E) =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
++tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e
+ tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi
+ tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi
+ tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi
+@@ -90,11 +90,11 @@ tune-$(CONFIG_CPU_ARM926T) =-mtune=arm9t
+ tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi
+ tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110
+ tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
+-tune-$(CONFIG_CPU_XSCALE) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+-tune-$(CONFIG_CPU_XSC3) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+-tune-$(CONFIG_CPU_FEROCEON) =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
+-tune-$(CONFIG_CPU_V6) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+-tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
++tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale
++tune-$(CONFIG_CPU_XSC3) =-mtune=xscale
++tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale
++tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s
++tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s
+
+ # Evaluate tune cc-option calls now
+ tune-y := $(tune-y)
--- /dev/null
+From a923a2676e60683aee46aa4b93c30aff240ac20d Mon Sep 17 00:00:00 2001
+From: "Maciej W. Rozycki" <macro@orcam.me.uk>
+Date: Fri, 22 Oct 2021 00:58:23 +0200
+Subject: MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL
+
+From: Maciej W. Rozycki <macro@orcam.me.uk>
+
+commit a923a2676e60683aee46aa4b93c30aff240ac20d upstream.
+
+Fix assembly errors like:
+
+{standard input}: Assembler messages:
+{standard input}:287: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
+{standard input}:680: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
+{standard input}:1274: Error: opcode not supported on this processor: mips3 (mips3) `dins $12,$9,32,32'
+{standard input}:2175: Error: opcode not supported on this processor: mips3 (mips3) `dins $10,$7,32,32'
+make[1]: *** [scripts/Makefile.build:277: mm/highmem.o] Error 1
+
+with code produced from `__cmpxchg64' for MIPS64r2 CPU configurations
+using CONFIG_32BIT and CONFIG_PHYS_ADDR_T_64BIT.
+
+This is due to MIPS_ISA_ARCH_LEVEL downgrading the assembly architecture
+to `r4000' i.e. MIPS III for MIPS64r2 configurations, while there is a
+block of code containing a DINS MIPS64r2 instruction conditionalized on
+MIPS_ISA_REV >= 2 within the scope of the downgrade.
+
+The assembly architecture override code pattern has been put there for
+LL/SC instructions, so that code compiles for configurations that select
+a processor to build for that does not support these instructions while
+still providing run-time support for processors that do, dynamically
+switched by non-constant `cpu_has_llsc'. It went in with linux-mips.org
+commit aac8aa7717a2 ("Enable a suitable ISA for the assembler around
+ll/sc so that code builds even for processors that don't support the
+instructions. Plus minor formatting fixes.") back in 2005.
+
+Fix the problem by wrapping these instructions along with the adjacent
+SYNC instructions only, following the practice established with commit
+cfd54de3b0e4 ("MIPS: Avoid move psuedo-instruction whilst using
+MIPS_ISA_LEVEL") and commit 378ed6f0e3c5 ("MIPS: Avoid using .set mips0
+to restore ISA"). Strictly speaking the SYNC instructions do not have
+to be wrapped as they are only used as a Loongson3 erratum workaround,
+so they will be enabled in the assembler by default, but do this so as
+to keep code consistent with other places.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
+Fixes: c7e2d71dda7a ("MIPS: Fix set_pte() for Netlogic XLR using cmpxchg64()")
+Cc: stable@vger.kernel.org # v5.1+
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/mips/include/asm/cmpxchg.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/include/asm/cmpxchg.h
++++ b/arch/mips/include/asm/cmpxchg.h
+@@ -249,6 +249,7 @@ static inline unsigned long __cmpxchg64(
+ /* Load 64 bits from ptr */
+ " " __SYNC(full, loongson3_war) " \n"
+ "1: lld %L0, %3 # __cmpxchg64 \n"
++ " .set pop \n"
+ /*
+ * Split the 64 bit value we loaded into the 2 registers that hold the
+ * ret variable.
+@@ -276,12 +277,14 @@ static inline unsigned long __cmpxchg64(
+ " or %L1, %L1, $at \n"
+ " .set at \n"
+ # endif
++ " .set push \n"
++ " .set " MIPS_ISA_ARCH_LEVEL " \n"
+ /* Attempt to store new at ptr */
+ " scd %L1, %2 \n"
+ /* If we failed, loop! */
+ "\t" __SC_BEQZ "%L1, 1b \n"
+- " .set pop \n"
+ "2: " __SYNC(full, loongson3_war) " \n"
++ " .set pop \n"
+ : "=&r"(ret),
+ "=&r"(tmp),
+ "=" GCC_OFF_SMALL_ASM() (*(unsigned long long *)ptr)
--- /dev/null
+From 279917e27edc293eb645a25428c6ab3f3bca3f86 Mon Sep 17 00:00:00 2001
+From: Helge Deller <deller@gmx.de>
+Date: Thu, 4 Nov 2021 20:19:00 +0100
+Subject: parisc: Fix backtrace to always include init funtion names
+
+From: Helge Deller <deller@gmx.de>
+
+commit 279917e27edc293eb645a25428c6ab3f3bca3f86 upstream.
+
+I noticed that sometimes at kernel startup the backtraces did not
+included the function names of init functions. Their address were not
+resolved to function names and instead only the address was printed.
+
+Debugging shows that the culprit is is_ksym_addr() which is called
+by the backtrace functions to check if an address belongs to a function in
+the kernel. The problem occurs only for CONFIG_KALLSYMS_ALL=y.
+
+When looking at is_ksym_addr() one can see that for CONFIG_KALLSYMS_ALL=y
+the function only tries to resolve the address via is_kernel() function,
+which checks like this:
+ if (addr >= _stext && addr <= _end)
+ return 1;
+On parisc the init functions are located before _stext, so this check fails.
+Other platforms seem to have all functions (including init functions)
+behind _stext.
+
+The following patch moves the _stext symbol at the beginning of the
+kernel and thus includes the init section. This fixes the check and does
+not seem to have any negative side effects on where the kernel mapping
+happens in the map_pages() function in arch/parisc/mm/init.c.
+
+Signed-off-by: Helge Deller <deller@gmx.de>
+Cc: stable@kernel.org # 5.4+
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/parisc/kernel/vmlinux.lds.S | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/parisc/kernel/vmlinux.lds.S
++++ b/arch/parisc/kernel/vmlinux.lds.S
+@@ -57,6 +57,8 @@ SECTIONS
+ {
+ . = KERNEL_BINARY_TEXT_START;
+
++ _stext = .; /* start of kernel text, includes init code & data */
++
+ __init_begin = .;
+ HEAD_TEXT_SECTION
+ MLONGCALL_DISCARD(INIT_TEXT_SECTION(8))
+@@ -80,7 +82,6 @@ SECTIONS
+ /* freed after init ends here */
+
+ _text = .; /* Text and read-only data */
+- _stext = .;
+ MLONGCALL_KEEP(INIT_TEXT_SECTION(8))
+ .text ALIGN(PAGE_SIZE) : {
+ TEXT_TEXT
net-smc-fix-sk_refcnt-underflow-on-linkdown-and-fall.patch
cxgb4-fix-eeprom-len-when-diagnostics-not-implemente.patch
selftests-net-udpgso_bench_rx-fix-port-argument.patch
+arm-9155-1-fix-early-early_iounmap.patch
+arm-9156-1-drop-cc-option-fallbacks-for-architecture-selection.patch
+parisc-fix-backtrace-to-always-include-init-funtion-names.patch
+mips-fix-assembly-error-from-mipsr2-code-used-within-mips_isa_arch_level.patch
+x86-mce-add-errata-workaround-for-skylake-skx37.patch
--- /dev/null
+From e629fc1407a63dbb748f828f9814463ffc2a0af0 Mon Sep 17 00:00:00 2001
+From: Dave Jones <davej@codemonkey.org.uk>
+Date: Fri, 29 Oct 2021 16:57:59 -0400
+Subject: x86/mce: Add errata workaround for Skylake SKX37
+
+From: Dave Jones <davej@codemonkey.org.uk>
+
+commit e629fc1407a63dbb748f828f9814463ffc2a0af0 upstream.
+
+Errata SKX37 is word-for-word identical to the other errata listed in
+this workaround. I happened to notice this after investigating a CMCI
+storm on a Skylake host. While I can't confirm this was the root cause,
+spurious corrected errors does sound like a likely suspect.
+
+Fixes: 2976908e4198 ("x86/mce: Do not log spurious corrected mce errors")
+Signed-off-by: Dave Jones <davej@codemonkey.org.uk>
+Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
+Reviewed-by: Tony Luck <tony.luck@intel.com>
+Cc: <stable@vger.kernel.org>
+Link: https://lkml.kernel.org/r/20211029205759.GA7385@codemonkey.org.uk
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/mce/intel.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/arch/x86/kernel/cpu/mce/intel.c
++++ b/arch/x86/kernel/cpu/mce/intel.c
+@@ -526,12 +526,13 @@ bool intel_filter_mce(struct mce *m)
+ {
+ struct cpuinfo_x86 *c = &boot_cpu_data;
+
+- /* MCE errata HSD131, HSM142, HSW131, BDM48, and HSM142 */
++ /* MCE errata HSD131, HSM142, HSW131, BDM48, HSM142 and SKX37 */
+ if ((c->x86 == 6) &&
+ ((c->x86_model == INTEL_FAM6_HASWELL) ||
+ (c->x86_model == INTEL_FAM6_HASWELL_L) ||
+ (c->x86_model == INTEL_FAM6_BROADWELL) ||
+- (c->x86_model == INTEL_FAM6_HASWELL_G)) &&
++ (c->x86_model == INTEL_FAM6_HASWELL_G) ||
++ (c->x86_model == INTEL_FAM6_SKYLAKE_X)) &&
+ (m->bank == 0) &&
+ ((m->status & 0xa0000000ffffffff) == 0x80000000000f0005))
+ return true;
projects / thirdparty / kernel / stable-queue.git / commitdiff
