+2012-10-17 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000.opt (rs6000_isa_flags): New flag word to
+ replace target_flags that gives us 63 possible switches.
+ (x_rs6000_isa_flags): Save area for rs6000_isa_flags.
+ (x_rs6000_isa_flags_explicit): Save area for
+ rs6000_isa_flags_explicit.
+ (rs6000_target_flags_explicit): Delete in favor of
+ x_rs6000_isa_flags_explicit.
+ (-mpowerpc64): Change all switches that used to be in target_flags
+ to now be in rs6000_isa_flags. In using rs6000_isa_flags, the
+ options machinary will generate names of the form OPITON_<xxx>
+ instead of TARGET_<xxx> and OPTION_MASK_<xxx> instead of
+ MASK_<xxx>.
+ (-mpowerpc-gpopt): Likewise.
+ (-mpowerpc-gfxopt): Likewise.
+ (-mmfcrf): Likewise.
+ (-mpopcntb): Likewise.
+ (-mfprnd): Likewise.
+ (-mcmpb): Likewise.
+ (-mmfpgpr): Likewise.
+ (-maltivec): Likewise.
+ (-mhard-dfp): Likewise.
+ (-mmulhw): Likewise.
+ (-mdlmzb): Likewise.
+ (-mmultiple): Likewise.
+ (-mstring): Likewise.
+ (-msoft-float): Likewise.
+ (-mhard-float): Likewise.
+ (-mpopcntd): Likewise.
+ (-mvsx): Likewise.
+ (-mno-update): Likewise.
+ (-mupdate): Likewise.
+ (-mrecip-precision): Likewise.
+ (-mminimal-toc): Likewise.
+ (-misel): Likewise.
+ * config/rs6000/aix64.opt (-maix64): Likewise.
+ (-maix32): Likewise.
+ * config/rs6000/sysv4.opt (-mstrict-align): Likewise.
+ (-mrelocatable): Likewise.
+ (-mlittle-endian): Likewise.
+ (-mlittle): Likewise.
+ (-mbig-endian): LIkewise.
+ (-mbig): Likewise.
+ (-meabi): Likewise.
+ (-m64): Likewise.
+ (-m32): Likewise.
+ * config/rs6000/darwin.opt (-m64): Likewise.
+ (-m32): Likewise.
+
+ * config/rs6000/rs6000-cpus.def (ISA_2_1_MASKS): Move the various
+ masks used in rs6000.c here, since they are more logically in this
+ file. Convert from being enums to just #defines, since the types
+ of these masks is now HOST_WIDE_INT instead of int. For
+ POWERPC_MASKS, add MASK_SOFT_FLOAT, since the only use case or'ed
+ in the mask. Change the use in rs6000.c not to do the OR of
+ MASK_SOFT_FLOAT.
+ (ISA_2_1_MASKS): Likewise.
+ (ISA_2_2_MASKS): Likewise.
+ (ISA_2_4_MASKS): Likewise.
+ (ISA_2_5_MASKS_EMBEDDED): Likewise.
+ (ISA_2_5_MASKS_SERVER): Likewise.
+ (POWERPC_7400_MASK): Likewise.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.c (ISA_2_1_MASKS): Likewise.
+ (ISA_2_1_MASKS): Likewise.
+ (ISA_2_2_MASKS): Likewise.
+ (ISA_2_4_MASKS): Likewise.
+ (ISA_2_5_MASKS_EMBEDDED): Likewise.
+ (ISA_2_5_MASKS_SERVER): Likewise.
+ (POWERPC_7400_MASK): Likewise.
+ (POWERPC_MASKS): Likewise.
+ (rs6000_option_override_internal): Likewise.
+
+ * config/rs6000/rs6000.c (darwin_rs6000_override_options): Change
+ all uses of target_flags to rs6000_isa_flags. Change all uses of
+ target_flags_explicit to rs6000_isa_flags_explicit. Change the
+ use of MASK_<xxx> to OPTION_MASK_<xxx> that options.h defines when
+ we use a secondary flags word. Save/restore/print the new flags
+ word when switching contexts with different target attributes.
+ (rs6000_option_override_internal): Likewise.
+ (rs6000_darwin_file_start): Likewise.
+ (rs6000_opt_masks): Likewise.
+ (rs6000_inner_target_options): Likewise.
+ (rs6000_pragma_target_parse): Likewise.
+ (rs6000_set_current_function): Likewise.
+ (rs6000_function_specific_save): Likewise.
+ (rs6000_function_specific_restore): Likewise.
+ (rs6000_function_specific_print): Likewise.
+ (rs6000_can_inline_p): Likewise.
+ * config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
+ Likewise.
+ (rs6000_cpu_cpp_builtins): Likewise.
+ * common/config/rs6000/rs6000-driver.c (rs6000_handle_option):
+ Likewise.
+
+ * config/rs6000/rs6000.h (MASK_ALTIVEC): In moving to using
+ Var(...) for all of the isa switches, the options machinery now
+ uses OPTION_MASK_<xxx> instead of MASK_<xxx> for the mask name.
+ Use #define to map the old name into the new name. For switches
+ that are defined in aix64.opt, sysv4.opt, and darwin.opt, only do
+ the definition if those switches were defined.
+ (MASK_ALTIVEC): Likewise.
+ (MASK_CMPB): Likewise.
+ (MASK_DFP): Likewise.
+ (MASK_DLMZB): Likewise.
+ (MASK_EABI): Likewise.
+ (MASK_FPRND): Likewise.
+ (MASK_HARD_FLOAT): Likewise.
+ (MASK_ISEL): Likewise.
+ (MASK_MFCRF): Likewise.
+ (MASK_MFPGPR): Likewise.
+ (MASK_MULHW): Likewise.
+ (MASK_MULTIPLE): Likewise.
+ (MASK_NO_UPDATE): Likewise.
+ (MASK_POPCNTB): Likewise.
+ (MASK_POPCNTD): Likewise.
+ (MASK_PPC_GFXOPT): Likewise.
+ (MASK_PPC_GPOPT): Likewise.
+ (MASK_RECIP_PRECISION): Likewise.
+ (MASK_SOFT_FLOAT): Likewise.
+ (MASK_STRICT_ALIGN): Likewise.
+ (MASK_STRING): Likewise.
+ (MASK_UPDATE): Likewise.
+ (MASK_VSX): Likewise.
+ (MASK_POWERPC64): Likewise.
+ (MASK_64BIT): Likewise.
+ (MASK_RELOCATABLE): Likewise.
+ (MASK_LITTLE_ENDIAN): Likewise.
+ (MASK_MINIMAL_TOC): Likewise.
+ (MASK_REGNAMES): Likewise.
+ (MASK_PROTOTYPE): Likewise.
+ (rs6000_isa_flags_explicit): Define in terms of the
+ global_options_set structure.
+
+ * gcc/config/rs6000/aix43.h (SUBTARGET_OVERRIDE_OPTIONS):
+ Change use of target_flags to rs6000_isa_flags,
+ target_flags_explicit to rs6000_isa_flags_explicit, and MASK_<xxx>
+ to OPTION_MASK_<xxx>.
+ * gcc/config/rs6000/aix51.h (SUBTARGET_OVERRIDE_OPTIONS):
+ Likewise.
+ * gcc/config/rs6000/aix52.h (SUBTARGET_OVERRIDE_OPTIONS):
+ Likewise.
+ * gcc/config/rs6000/aix53.h (SUBTARGET_OVERRIDE_OPTIONS):
+ Likewise.
+ * gcc/config/rs6000/aix61.h (SUBTARGET_OVERRIDE_OPTIONS):
+ Likewise.
+ * gcc/config/rs6000/freebsd64.h (RELOCATABLE_NEEDS_FIXUP):
+ Likewise.
+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise.
+ * gcc/config/rs6000/freebsd.h (RELOCATABLE_NEEDS_FIXUP):
+ Likewise.
+ * gcc/config/rs6000/linux64.h (RELOCATABLE_NEEDS_FIXUP):
+ Likewise.
+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise.
+ (OPTION_LITTLE_ENDIAN): Likewise.
+ (OPTION_RELOCATABLE): Likewise.
+ (OPTION_EABI): Likewise.
+ (OPTION_PROTOTYPE): Likewise.
+ * gcc/config/rs6000/linux.h (RELOCATABLE_NEEDS_FIXUP): Likewise.
+ * gcc/config/rs6000/option-defaults.h (OPTION_MASK_64BIT):
+ Likewise.
+ (OPT_ARCH32): Likewise.
+ (OPT_ARCH64): Likewise.
+ * gcc/config/rs6000/sysv4.h (TARGET_TOC): Likewise.
+ (SUBTARGET_OVERRIDE_OPTIONS): Likewise.
+ (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise.
+ (TARGET_OS_SYSV_CPP_BUILTINS): Likewise.
+
+ * config/rs6000/t-rs6000 (rs6000.o): Add rs6000-cpus.def as a
+ dependency.
+
2012-10-17 Jan Hubicka <jh@suse.cz>
* cfgloopmanip.c (copy_loop_info): New function.
switch (code)
{
case OPT_mfull_toc:
- opts->x_target_flags &= ~MASK_MINIMAL_TOC;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_MINIMAL_TOC;
opts->x_TARGET_NO_FP_IN_TOC = 0;
opts->x_TARGET_NO_SUM_IN_TOC = 0;
- opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
#ifdef TARGET_USES_SYSV4_OPT
/* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
just the same as -mminimal-toc. */
- opts->x_target_flags |= MASK_MINIMAL_TOC;
- opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+ opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
#endif
break;
#ifdef TARGET_USES_SYSV4_OPT
case OPT_mtoc:
/* Make -mtoc behave like -mminimal-toc. */
- opts->x_target_flags |= MASK_MINIMAL_TOC;
- opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+ opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
break;
#endif
#else
case OPT_m64:
#endif
- opts->x_target_flags |= MASK_POWERPC64;
- opts->x_target_flags |= ~opts_set->x_target_flags & MASK_PPC_GFXOPT;
- opts_set->x_target_flags |= MASK_POWERPC64;
+ opts->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
+ opts->x_rs6000_isa_flags |= (~opts_set->x_rs6000_isa_flags
+ & OPTION_MASK_PPC_GFXOPT);
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
break;
#ifdef TARGET_USES_AIX64_OPT
#else
case OPT_m32:
#endif
- opts->x_target_flags &= ~MASK_POWERPC64;
- opts_set->x_target_flags |= MASK_POWERPC64;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_POWERPC64;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_POWERPC64;
break;
case OPT_mminimal_toc:
case OPT_mrelocatable:
if (value == 1)
{
- opts->x_target_flags |= MASK_MINIMAL_TOC;
- opts_set->x_target_flags |= MASK_MINIMAL_TOC;
+ opts->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC;
opts->x_TARGET_NO_FP_IN_TOC = 1;
}
break;
case OPT_mrelocatable_lib:
if (value == 1)
{
- opts->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
- opts_set->x_target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
+ opts->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
+ | OPTION_MASK_MINIMAL_TOC);
+ opts_set->x_rs6000_isa_flags |= (OPTION_MASK_RELOCATABLE
+ | OPTION_MASK_MINIMAL_TOC);
opts->x_TARGET_NO_FP_IN_TOC = 1;
}
else
{
- opts->x_target_flags &= ~MASK_RELOCATABLE;
- opts_set->x_target_flags |= MASK_RELOCATABLE;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_RELOCATABLE;
}
break;
#endif
"-msingle-float option equivalent to -mhard-float");
/* -msingle-float implies -mno-double-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_double_float = 0;
- opts->x_target_flags &= ~MASK_SOFT_FLOAT;
- opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_mdouble_float:
/* -mdouble-float implies -msingle-float and TARGET_HARD_FLOAT. */
opts->x_rs6000_single_float = 1;
- opts->x_target_flags &= ~MASK_SOFT_FLOAT;
- opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
break;
case OPT_msimple_fpu:
{
/* If -mfpu is not none, then turn off SOFT_FLOAT, turn on
HARD_FLOAT. */
- opts->x_target_flags &= ~MASK_SOFT_FLOAT;
- opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+ opts->x_rs6000_isa_flags &= ~OPTION_MASK_SOFT_FLOAT;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_xilinx_fpu = 1;
if (fpu_type == FPU_SF_LITE || fpu_type == FPU_SF_FULL)
opts->x_rs6000_single_float = 1;
else
{
/* -mfpu=none is equivalent to -msoft-float. */
- opts->x_target_flags |= MASK_SOFT_FLOAT;
- opts_set->x_target_flags |= MASK_SOFT_FLOAT;
+ opts->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
+ opts_set->x_rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
opts->x_rs6000_single_float = opts->x_rs6000_double_float = 0;
}
break;
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE rs6000_option_optimization_table
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
- (TARGET_DEFAULT)
-
struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_POWERPC64 && ! TARGET_64BIT) \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
do { \
if (TARGET_64BIT && ! TARGET_POWERPC64) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
warning (0, "-maix64 requires PowerPC64 architecture remain enabled"); \
} \
if (TARGET_SOFT_FLOAT && TARGET_LONG_DOUBLE_128) \
; <http://www.gnu.org/licenses/>.
maix64
-Target Report RejectNegative Negative(maix32) Mask(64BIT)
+Target Report RejectNegative Negative(maix32) Mask(64BIT) Var(rs6000_isa_flags)
Compile for 64-bit pointers
maix32
-Target Report RejectNegative Negative(maix64) InverseMask(64BIT)
+Target Report RejectNegative Negative(maix64) InverseMask(64BIT) Var(rs6000_isa_flags)
Compile for 32-bit pointers
mpe
Driver RejectNegative Alias(mfix-and-continue)
m64
-Target RejectNegative Negative(m32) Mask(64BIT)
+Target RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code
m32
-Target RejectNegative Negative(m64) InverseMask(64BIT)
+Target RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
- (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+ (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
- (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+ (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#undef RS6000_ABI_NAME
#define RS6000_ABI_NAME "freebsd"
error (INVALID_64BIT, "call"); \
} \
dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \
- if (target_flags & MASK_RELOCATABLE) \
+ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
{ \
- target_flags &= ~MASK_RELOCATABLE; \
+ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
error (INVALID_64BIT, "relocatable"); \
} \
- if (target_flags & MASK_EABI) \
+ if (rs6000_isa_flags & OPTION_MASK_EABI) \
{ \
- target_flags &= ~MASK_EABI; \
+ rs6000_isa_flags &= ~OPTION_MASK_EABI; \
error (INVALID_64BIT, "eabi"); \
} \
if (TARGET_PROTOTYPE) \
target_prototype = 0; \
error (INVALID_64BIT, "prototype"); \
} \
- if ((target_flags & MASK_POWERPC64) == 0) \
+ if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
error ("-m64 requires a PowerPC64 cpu"); \
} \
- if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \
+ if ((rs6000_isa_flags_explicit \
+ & OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
- (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+ (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#define TARGET_POSIX_IO
-mrelocatable or -mrelocatable-lib is given. */
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP \
- (target_flags & target_flags_explicit & MASK_RELOCATABLE)
+ (rs6000_isa_flags & rs6000_isa_flags_explicit & OPTION_MASK_RELOCATABLE)
#undef RS6000_ABI_NAME
#define RS6000_ABI_NAME "linux"
error (INVALID_64BIT, "call"); \
} \
dot_symbols = !strcmp (rs6000_abi_name, "aixdesc"); \
- if (target_flags & MASK_RELOCATABLE) \
+ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
{ \
- target_flags &= ~MASK_RELOCATABLE; \
+ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
error (INVALID_64BIT, "relocatable"); \
} \
- if (target_flags & MASK_EABI) \
+ if (rs6000_isa_flags & OPTION_MASK_EABI) \
{ \
- target_flags &= ~MASK_EABI; \
+ rs6000_isa_flags &= ~OPTION_MASK_EABI; \
error (INVALID_64BIT, "eabi"); \
} \
if (TARGET_PROTOTYPE) \
target_prototype = 0; \
error (INVALID_64BIT, "prototype"); \
} \
- if ((target_flags & MASK_POWERPC64) == 0) \
+ if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \
{ \
- target_flags |= MASK_POWERPC64; \
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
error ("-m64 requires a PowerPC64 cpu"); \
} \
- if ((target_flags_explicit & MASK_MINIMAL_TOC) != 0) \
+ if ((rs6000_isa_flags_explicit \
+ & OPTION_MASK_MINIMAL_TOC) != 0) \
{ \
if (global_options_set.x_rs6000_current_cmodel \
&& rs6000_current_cmodel != CMODEL_SMALL) \
#ifndef RS6000_BI_ARCH
/* 64-bit PowerPC Linux is always big-endian. */
-#undef TARGET_LITTLE_ENDIAN
-#define TARGET_LITTLE_ENDIAN 0
+#undef OPTION_LITTLE_ENDIAN
+#define OPTION_LITTLE_ENDIAN 0
/* 64-bit PowerPC Linux always has a TOC. */
#undef TARGET_TOC
#define TARGET_TOC 1
/* Some things from sysv4.h we don't do when 64 bit. */
-#undef TARGET_RELOCATABLE
-#define TARGET_RELOCATABLE 0
-#undef TARGET_EABI
-#define TARGET_EABI 0
-#undef TARGET_PROTOTYPE
-#define TARGET_PROTOTYPE 0
+#undef OPTION_RELOCATABLE
+#define OPTION_RELOCATABLE 0
+#undef OPTION_EABI
+#define OPTION_EABI 0
+#undef OPTION_PROTOTYPE
+#define OPTION_PROTOTYPE 0
#undef RELOCATABLE_NEEDS_FIXUP
#define RELOCATABLE_NEEDS_FIXUP 0
#define OPT_32 "m32"
#endif
-#ifndef MASK_64BIT
+#ifndef OPTION_MASK_64BIT
+#define OPTION_MASK_64BIT 0
#define MASK_64BIT 0
#endif
-#if TARGET_DEFAULT & MASK_64BIT
+#if TARGET_DEFAULT & OPTION_MASK_64BIT
#define OPT_ARCH64 "!"OPT_32
#define OPT_ARCH32 OPT_32
#else
(define_p) ? "define" : "undef",
flags, bu_mask);
- /* target_flags based options. */
+ /* rs6000_isa_flags based options. */
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC");
- if ((flags & MASK_PPC_GPOPT) != 0)
+ if ((flags & OPTION_MASK_PPC_GPOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ");
- if ((flags & MASK_PPC_GFXOPT) != 0)
+ if ((flags & OPTION_MASK_PPC_GFXOPT) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR");
- if ((flags & MASK_POWERPC64) != 0)
+ if ((flags & OPTION_MASK_POWERPC64) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64");
- if ((flags & MASK_MFCRF) != 0)
+ if ((flags & OPTION_MASK_MFCRF) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4");
- if ((flags & MASK_POPCNTB) != 0)
+ if ((flags & OPTION_MASK_POPCNTB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5");
- if ((flags & MASK_FPRND) != 0)
+ if ((flags & OPTION_MASK_FPRND) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X");
- if ((flags & MASK_CMPB) != 0)
+ if ((flags & OPTION_MASK_CMPB) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6");
- if ((flags & MASK_MFPGPR) != 0)
+ if ((flags & OPTION_MASK_MFPGPR) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X");
- if ((flags & MASK_POPCNTD) != 0)
+ if ((flags & OPTION_MASK_POPCNTD) != 0)
rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7");
- if ((flags & MASK_SOFT_FLOAT) != 0)
+ if ((flags & OPTION_MASK_SOFT_FLOAT) != 0)
rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT");
- if ((flags & MASK_RECIP_PRECISION) != 0)
+ if ((flags & OPTION_MASK_RECIP_PRECISION) != 0)
rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__");
- if ((flags & MASK_ALTIVEC) != 0)
+ if ((flags & OPTION_MASK_ALTIVEC) != 0)
{
const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__";
rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__");
if (!flag_iso)
rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__");
}
- if ((flags & MASK_VSX) != 0)
+ if ((flags & OPTION_MASK_VSX) != 0)
rs6000_define_or_undefine_macro (define_p, "__VSX__");
/* options from the builtin masks. */
rs6000_cpu_cpp_builtins (cpp_reader *pfile)
{
/* Define all of the common macros. */
- rs6000_target_modify_macros (true, target_flags,
+ rs6000_target_modify_macros (true, rs6000_isa_flags,
rs6000_builtin_mask_calculate ());
if (TARGET_FRE)
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+/* ISA masks. */
+#ifndef ISA_2_1_MASKS
+#define ISA_2_1_MASKS OPTION_MASK_MFCRF
+#define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
+#define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
+
+ /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
+ ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
+ fre, fsqrt, etc. were no longer documented as optional. Group masks by
+ server and embedded. */
+#define ISA_2_5_MASKS_EMBEDDED (ISA_2_2_MASKS \
+ | OPTION_MASK_CMPB \
+ | OPTION_MASK_RECIP_PRECISION \
+ | OPTION_MASK_PPC_GFXOPT \
+ | OPTION_MASK_PPC_GPOPT)
+
+#define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
+
+ /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
+ altivec is a win so enable it. */
+#define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
+#define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
+ | OPTION_MASK_POPCNTD \
+ | OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_VSX)
+
+#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
+
+/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
+#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_CMPB \
+ | OPTION_MASK_DFP \
+ | OPTION_MASK_DLMZB \
+ | OPTION_MASK_FPRND \
+ | OPTION_MASK_ISEL \
+ | OPTION_MASK_MFCRF \
+ | OPTION_MASK_MFPGPR \
+ | OPTION_MASK_MULHW \
+ | OPTION_MASK_NO_UPDATE \
+ | OPTION_MASK_POPCNTB \
+ | OPTION_MASK_POPCNTD \
+ | OPTION_MASK_POWERPC64 \
+ | OPTION_MASK_PPC_GFXOPT \
+ | OPTION_MASK_PPC_GPOPT \
+ | OPTION_MASK_RECIP_PRECISION \
+ | OPTION_MASK_SOFT_FLOAT \
+ | OPTION_MASK_STRICT_ALIGN \
+ | OPTION_MASK_VSX)
+
+#endif
+
/* This table occasionally claims that a processor does not support a
particular feature even though it does, but the feature is slower than the
alternative. Thus, it shouldn't be relied on as a complete description of
{ NULL, 0, 0, false, false, false, NULL, false }
};
\f
-#ifndef MASK_STRICT_ALIGN
+#ifndef OPTION_MASK_STRICT_ALIGN
+#define OPTION_MASK_STRICT_ALIGN 0
#define MASK_STRICT_ALIGN 0
#endif
#ifndef TARGET_PROFILE_KERNEL
#define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
\f
-/* Simplifications for entries below. */
-
-enum {
- POWERPC_7400_MASK = MASK_PPC_GFXOPT | MASK_ALTIVEC
-};
-
-/* Some OSs don't support saving the high part of 64-bit registers on context
- switch. Other OSs don't support saving Altivec registers. On those OSs, we
- don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
- either, the user must explicitly specify them and we won't interfere with
- the user's specification. */
-
-enum {
- POWERPC_MASKS = (MASK_PPC_GPOPT | MASK_STRICT_ALIGN
- | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
- | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
- | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
- | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
- | MASK_RECIP_PRECISION)
-};
-
-/* Masks for instructions set at various powerpc ISAs. */
-enum {
- ISA_2_1_MASKS = MASK_MFCRF,
- ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
- ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
-
- /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
- ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
- fre, fsqrt, etc. were no longer documented as optional. Group masks by
- server and embedded. */
- ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
- | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
- ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
-
- /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
- altivec is a win so enable it. */
- ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
- ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
- | MASK_VSX)
-};
-
+/* Processor table. */
struct rs6000_ptt
{
const char *const name; /* Canonical processor name. */
if (TARGET_64BIT && ! TARGET_POWERPC64)
{
- target_flags |= MASK_POWERPC64;
+ rs6000_isa_flags |= OPTION_MASK_POWERPC64;
warning (0, "-m64 requires PowerPC64 architecture, enabling");
}
if (flag_mkernel)
{
rs6000_default_long_calls = 1;
- target_flags |= MASK_SOFT_FLOAT;
+ rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
}
/* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
Altivec. */
if (!flag_mkernel && !flag_apple_kext
&& TARGET_64BIT
- && ! (target_flags_explicit & MASK_ALTIVEC))
- target_flags |= MASK_ALTIVEC;
+ && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
+ rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
/* Unless the user (not the configurer) has explicitly overridden
it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
if (!flag_mkernel
&& !flag_apple_kext
&& strverscmp (darwin_macosx_version_min, "10.5") >= 0
- && ! (target_flags_explicit & MASK_ALTIVEC)
+ && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
&& ! global_options_set.x_rs6000_cpu_index)
{
- target_flags |= MASK_ALTIVEC;
+ rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
}
}
#endif
rs6000_pointer_size = 32;
}
- set_masks = POWERPC_MASKS | MASK_SOFT_FLOAT;
+ /* Some OSs don't support saving the high part of 64-bit registers on context
+ switch. Other OSs don't support saving Altivec registers. On those OSs,
+ we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
+ if the user wants either, the user must explicitly specify them and we
+ won't interfere with the user's specification. */
+
+ set_masks = POWERPC_MASKS;
#ifdef OS_MISSING_POWERPC64
if (OS_MISSING_POWERPC64)
- set_masks &= ~MASK_POWERPC64;
+ set_masks &= ~OPTION_MASK_POWERPC64;
#endif
#ifdef OS_MISSING_ALTIVEC
if (OS_MISSING_ALTIVEC)
- set_masks &= ~MASK_ALTIVEC;
+ set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
#endif
/* Don't override by the processor default if given explicitly. */
- set_masks &= ~target_flags_explicit;
+ set_masks &= ~rs6000_isa_flags_explicit;
/* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
the cpu in a target attribute or pragma, but did not specify a tuning
TARGET_DEFAULT. */
if (have_cpu)
{
- target_flags &= ~set_masks;
- target_flags |= (processor_target_table[cpu_index].target_enable
- & set_masks);
+ rs6000_isa_flags &= ~set_masks;
+ rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
+ & set_masks);
}
else
- target_flags |= (processor_target_table[cpu_index].target_enable
- & ~target_flags_explicit);
+ rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
+ & ~rs6000_isa_flags_explicit);
+
+ /* If no -mcpu=<xxx>, inherit any default options that were cleared via
+ POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
+ target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
+ to using rs6000_isa_flags, we need to do the initialization here. */
+ if (!have_cpu)
+ rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit);
if (rs6000_tune_index >= 0)
tune_index = rs6000_tune_index;
use instructions that would be microcoded on the Cell, use the
load/store multiple and string instructions. */
if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
- target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
+ rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
+ | OPTION_MASK_STRING);
/* Don't allow -mmultiple or -mstring on little endian systems
unless the cpu is a 750, because the hardware doesn't support the
{
if (TARGET_MULTIPLE)
{
- target_flags &= ~MASK_MULTIPLE;
- if ((target_flags_explicit & MASK_MULTIPLE) != 0)
+ rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
warning (0, "-mmultiple is not supported on little endian systems");
}
if (TARGET_STRING)
{
- target_flags &= ~MASK_STRING;
- if ((target_flags_explicit & MASK_STRING) != 0)
+ rs6000_isa_flags &= ~OPTION_MASK_STRING;
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
warning (0, "-mstring is not supported on little endian systems");
}
}
if (!TARGET_HARD_FLOAT || !TARGET_FPRS
|| !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
{
- if (target_flags_explicit & MASK_VSX)
+ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx requires hardware floating point");
else
- target_flags &= ~ MASK_VSX;
+ rs6000_isa_flags &= ~ OPTION_MASK_VSX;
}
else if (TARGET_PAIRED_FLOAT)
msg = N_("-mvsx and -mpaired are incompatible");
msg = N_("-mvsx used with little endian code");
else if (TARGET_AVOID_XFORM > 0)
msg = N_("-mvsx needs indexed addressing");
- else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
+ else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
+ & OPTION_MASK_ALTIVEC))
{
- if (target_flags_explicit & MASK_VSX)
+ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
msg = N_("-mvsx and -mno-altivec are incompatible");
else
msg = N_("-mno-altivec disables vsx");
if (msg)
{
warning (0, msg);
- target_flags &= ~ MASK_VSX;
- target_flags_explicit |= MASK_VSX;
+ rs6000_isa_flags &= ~ OPTION_MASK_VSX;
+ rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
}
}
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
if (TARGET_VSX)
- target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_POPCNTD)
- target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
else if (TARGET_DFP)
- target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_CMPB)
- target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
else if (TARGET_FPRND)
- target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
else if (TARGET_POPCNTB)
- target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
+ rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
else if (TARGET_ALTIVEC)
- target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
+ rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
/* E500mc does "better" if we inline more aggressively. Respect the
user's opinion, though. */
unless the altivec ABI was set. This is set by default for 64-bit, but
not for 32-bit. */
if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
- target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
+ rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
+ & ~rs6000_isa_flags_explicit);
/* Enable Altivec ABI for AIX -maltivec. */
if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
rs6000_double_float = TARGET_E500_DOUBLE;
- target_flags &= ~MASK_STRING;
+ rs6000_isa_flags &= ~OPTION_MASK_STRING;
break;
default:
- if (have_cpu && !(target_flags_explicit & MASK_ISEL))
- target_flags &= ~MASK_ISEL;
+ if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
+ rs6000_isa_flags &= ~OPTION_MASK_ISEL;
break;
}
i = 0;
while (mapping[i].arg != NULL
&& strcmp (mapping[i].arg, cpu_id) != 0
- && (mapping[i].if_set & target_flags) == 0)
+ && (mapping[i].if_set & rs6000_isa_flags) == 0)
i++;
fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
static struct rs6000_opt_mask const rs6000_opt_masks[] =
{
- { "altivec", MASK_ALTIVEC, false, true },
- { "cmpb", MASK_CMPB, false, true },
- { "dlmzb", MASK_DLMZB, false, true },
- { "fprnd", MASK_FPRND, false, true },
- { "hard-dfp", MASK_DFP, false, true },
- { "isel", MASK_ISEL, false, true },
- { "mfcrf", MASK_MFCRF, false, true },
- { "mfpgpr", MASK_MFPGPR, false, true },
- { "mulhw", MASK_MULHW, false, true },
- { "multiple", MASK_MULTIPLE, false, true },
- { "update", MASK_NO_UPDATE, true , true },
- { "popcntb", MASK_POPCNTB, false, true },
- { "popcntd", MASK_POPCNTD, false, true },
- { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
- { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
- { "recip-precision", MASK_RECIP_PRECISION, false, true },
- { "string", MASK_STRING, false, true },
- { "vsx", MASK_VSX, false, true },
-#ifdef MASK_64BIT
+ { "altivec", OPTION_MASK_ALTIVEC, false, true },
+ { "cmpb", OPTION_MASK_CMPB, false, true },
+ { "dlmzb", OPTION_MASK_DLMZB, false, true },
+ { "fprnd", OPTION_MASK_FPRND, false, true },
+ { "hard-dfp", OPTION_MASK_DFP, false, true },
+ { "isel", OPTION_MASK_ISEL, false, true },
+ { "mfcrf", OPTION_MASK_MFCRF, false, true },
+ { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
+ { "mulhw", OPTION_MASK_MULHW, false, true },
+ { "multiple", OPTION_MASK_MULTIPLE, false, true },
+ { "update", OPTION_MASK_NO_UPDATE, true , true },
+ { "popcntb", OPTION_MASK_POPCNTB, false, true },
+ { "popcntd", OPTION_MASK_POPCNTD, false, true },
+ { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
+ { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
+ { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
+ { "string", OPTION_MASK_STRING, false, true },
+ { "vsx", OPTION_MASK_VSX, false, true },
+#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
- { "aix64", MASK_64BIT, false, false },
- { "aix32", MASK_64BIT, true, false },
+ { "aix64", OPTION_MASK_64BIT, false, false },
+ { "aix32", OPTION_MASK_64BIT, true, false },
#else
- { "64", MASK_64BIT, false, false },
- { "32", MASK_64BIT, true, false },
+ { "64", OPTION_MASK_64BIT, false, false },
+ { "32", OPTION_MASK_64BIT, true, false },
#endif
#endif
-#ifdef MASK_EABI
- { "eabi", MASK_EABI, false, false },
+#ifdef OPTION_MASK_EABI
+ { "eabi", OPTION_MASK_EABI, false, false },
#endif
-#ifdef MASK_LITTLE_ENDIAN
- { "little", MASK_LITTLE_ENDIAN, false, false },
- { "big", MASK_LITTLE_ENDIAN, true, false },
+#ifdef OPTION_MASK_LITTLE_ENDIAN
+ { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
+ { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
#endif
-#ifdef MASK_RELOCATABLE
- { "relocatable", MASK_RELOCATABLE, false, false },
+#ifdef OPTION_MASK_RELOCATABLE
+ { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
#endif
-#ifdef MASK_STRICT_ALIGN
- { "strict-align", MASK_STRICT_ALIGN, false, false },
+#ifdef OPTION_MASK_STRICT_ALIGN
+ { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
#endif
- { "soft-float", MASK_SOFT_FLOAT, false, false },
- { "string", MASK_STRING, false, false },
+ { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
+ { "string", OPTION_MASK_STRING, false, false },
};
/* Builtin mask mapping for printing the flags. */
else
{
error_p = false;
- target_flags_explicit |= mask;
+ rs6000_isa_flags_explicit |= mask;
/* VSX needs altivec, so -mvsx automagically sets
altivec. */
- if (mask == MASK_VSX && !invert)
- mask |= MASK_ALTIVEC;
+ if (mask == OPTION_MASK_VSX && !invert)
+ mask |= OPTION_MASK_ALTIVEC;
if (rs6000_opt_masks[i].invert)
invert = !invert;
if (invert)
- target_flags &= ~mask;
+ rs6000_isa_flags &= ~mask;
else
- target_flags |= mask;
+ rs6000_isa_flags |= mask;
}
break;
}
{
prev_opt = TREE_TARGET_OPTION (prev_tree);
prev_bumask = prev_opt->x_rs6000_builtin_mask;
- prev_flags = prev_opt->x_target_flags;
+ prev_flags = prev_opt->x_rs6000_isa_flags;
cur_opt = TREE_TARGET_OPTION (cur_tree);
- cur_flags = cur_opt->x_target_flags;
+ cur_flags = cur_opt->x_rs6000_isa_flags;
cur_bumask = cur_opt->x_rs6000_builtin_mask;
diff_bumask = (prev_bumask ^ cur_bumask);
- diff_flags = (prev_flags ^ cur_flags);
+ diff_flags = (prev_flags ^ cur_flags);
if ((diff_flags != 0) || (diff_bumask != 0))
{
static void
rs6000_function_specific_save (struct cl_target_option *ptr)
{
- ptr->rs6000_target_flags_explicit = target_flags_explicit;
+ ptr->x_rs6000_isa_flags = rs6000_isa_flags;
+ ptr->x_rs6000_isa_flags_explicit = rs6000_isa_flags_explicit;
}
/* Restore the current options */
static void
rs6000_function_specific_restore (struct cl_target_option *ptr)
{
- target_flags_explicit = ptr->rs6000_target_flags_explicit;
+ rs6000_isa_flags = ptr->x_rs6000_isa_flags;
+ rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
(void) rs6000_option_override_internal (false);
}
struct cl_target_option *ptr)
{
rs6000_print_isa_options (file, indent, "Isa options set",
- ptr->x_target_flags);
+ ptr->x_rs6000_isa_flags);
rs6000_print_isa_options (file, indent, "Isa options explicit",
- ptr->rs6000_target_flags_explicit);
+ ptr->x_rs6000_isa_flags_explicit);
}
/* Helper function to print the current isa or misc options on a line. */
/* Callee's options should a subset of the caller's, i.e. a vsx function
can inline an altivec function but a non-vsx function can't inline a
vsx function. */
- if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
- == callee_opts->x_target_flags)
+ if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
+ == callee_opts->x_rs6000_isa_flags)
ret = true;
}
#define TARGET_FCTIDUZ TARGET_POPCNTD
#define TARGET_FCTIWUZ TARGET_POPCNTD
+/* In switching from using target_flags to using rs6000_isa_flags, the options
+ machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
+ OPTION_MASK_<xxx> back into MASK_<xxx>. */
+#define MASK_ALTIVEC OPTION_MASK_ALTIVEC
+#define MASK_CMPB OPTION_MASK_CMPB
+#define MASK_DFP OPTION_MASK_DFP
+#define MASK_DLMZB OPTION_MASK_DLMZB
+#define MASK_EABI OPTION_MASK_EABI
+#define MASK_FPRND OPTION_MASK_FPRND
+#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
+#define MASK_ISEL OPTION_MASK_ISEL
+#define MASK_MFCRF OPTION_MASK_MFCRF
+#define MASK_MFPGPR OPTION_MASK_MFPGPR
+#define MASK_MULHW OPTION_MASK_MULHW
+#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
+#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
+#define MASK_POPCNTB OPTION_MASK_POPCNTB
+#define MASK_POPCNTD OPTION_MASK_POPCNTD
+#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
+#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
+#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
+#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
+#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
+#define MASK_STRING OPTION_MASK_STRING
+#define MASK_UPDATE OPTION_MASK_UPDATE
+#define MASK_VSX OPTION_MASK_VSX
+
+#ifndef IN_LIBGCC2
+#define MASK_POWERPC64 OPTION_MASK_POWERPC64
+#endif
+
+#ifdef TARGET_64BIT
+#define MASK_64BIT OPTION_MASK_64BIT
+#endif
+
+#ifdef TARGET_RELOCATABLE
+#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE
+#endif
+
+#ifdef TARGET_LITTLE_ENDIAN
+#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
+#endif
+
+#ifdef TARGET_MINIMAL_TOC
+#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC
+#endif
+
+#ifdef TARGET_REGNAMES
+#define MASK_REGNAMES OPTION_MASK_REGNAMES
+#endif
+
+#ifdef TARGET_PROTOTYPE
+#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
+#endif
+
+/* Explicit ISA options that were set. */
+#define rs6000_isa_flags_explicit global_options_set.x_rs6000_isa_flags
+
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
HeaderInclude
config/rs6000/rs6000-opts.h
+;; ISA flag bits (on/off)
+Variable
+HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
+
+TargetSave
+HOST_WIDE_INT x_rs6000_isa_flags
+
+;; Miscellaneous flag bits that were set explicitly by the user
+TargetSave
+HOST_WIDE_INT x_rs6000_isa_flags_explicit
+
;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603
TargetVariable
unsigned int rs6000_debug
-;; Save for target_flags_explicit
-TargetSave
-int rs6000_target_flags_explicit
-
;; This option existed in the past, but now is always on.
mpowerpc
Target RejectNegative Undocumented Ignore
mpowerpc64
-Target Report Mask(POWERPC64)
+Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set
mpowerpc-gpopt
-Target Report Mask(PPC_GPOPT) Save
+Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions
mpowerpc-gfxopt
-Target Report Mask(PPC_GFXOPT) Save
+Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions
mmfcrf
-Target Report Mask(MFCRF) Save
+Target Report Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction
mpopcntb
-Target Report Mask(POPCNTB) Save
+Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction
mfprnd
-Target Report Mask(FPRND) Save
+Target Report Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions
mcmpb
-Target Report Mask(CMPB) Save
+Target Report Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction
mmfpgpr
-Target Report Mask(MFPGPR) Save
+Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
Use extended PowerPC V2.05 move floating point to/from GPR instructions
maltivec
-Target Report Mask(ALTIVEC) Save
+Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions
mhard-dfp
-Target Report Mask(DFP) Save
+Target Report Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions
mmulhw
-Target Report Mask(MULHW) Save
+Target Report Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions
mdlmzb
-Target Report Mask(DLMZB) Save
+Target Report Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction
mmultiple
-Target Report Mask(MULTIPLE) Save
+Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions
mstring
-Target Report Mask(STRING) Save
+Target Report Mask(STRING) Var(rs6000_isa_flags)
Generate string instructions for block moves
msoft-float
-Target Report RejectNegative Mask(SOFT_FLOAT)
+Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point
mhard-float
-Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT)
+Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point
mpopcntd
-Target Report Mask(POPCNTD) Save
+Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction
mfriz
Vector library ABI to use
mvsx
-Target Report Mask(VSX) Save
+Target Report Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions
mvsx-scalar-double
; Explicitly control whether we vectorize the builtins or not.
mno-update
-Target Report RejectNegative Mask(NO_UPDATE) Save
+Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions
mupdate
-Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE)
+Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions
msingle-pic-base
Generate software reciprocal divide and square root for better throughput.
mrecip-precision
-Target Report Mask(RECIP_PRECISION) Save
+Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy.
mno-fp-in-toc
; This is at the cost of having 2 extra loads and one extra store per
; function, and one less allocable register.
mminimal-toc
-Target Report Mask(MINIMAL_TOC)
+Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure
mfull-toc
Specify how many bytes should be moved inline before calling out to memcpy/memmove
misel
-Target Report Mask(ISEL) Save
+Target Report Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions
misel=no
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc"
-#define TARGET_TOC ((target_flags & MASK_64BIT) \
- || ((target_flags & (MASK_RELOCATABLE \
- | MASK_MINIMAL_TOC)) \
+#define TARGET_TOC ((rs6000_isa_flags & OPTION_MASK_64BIT) \
+ || ((rs6000_isa_flags \
+ & (OPTION_MASK_RELOCATABLE \
+ | OPTION_MASK_MINIMAL_TOC)) \
&& flag_pic > 1) \
|| DEFAULT_ABI == ABI_AIX)
else if (!strcmp (rs6000_abi_name, "sysv-noeabi")) \
{ \
rs6000_current_abi = ABI_V4; \
- target_flags &= ~ MASK_EABI; \
+ rs6000_isa_flags &= ~ OPTION_MASK_EABI; \
} \
else if (!strcmp (rs6000_abi_name, "sysv-eabi") \
|| !strcmp (rs6000_abi_name, "eabi")) \
{ \
rs6000_current_abi = ABI_V4; \
- target_flags |= MASK_EABI; \
+ rs6000_isa_flags |= OPTION_MASK_EABI; \
} \
else if (!strcmp (rs6000_abi_name, "aixdesc")) \
rs6000_current_abi = ABI_AIX; \
else if (!strcmp (rs6000_abi_name, "i960-old")) \
{ \
rs6000_current_abi = ABI_V4; \
- target_flags |= (MASK_LITTLE_ENDIAN | MASK_EABI); \
- target_flags &= ~MASK_STRICT_ALIGN; \
+ rs6000_isa_flags |= (OPTION_MASK_LITTLE_ENDIAN | OPTION_MASK_EABI); \
+ rs6000_isa_flags &= ~OPTION_MASK_STRICT_ALIGN; \
TARGET_NO_BITFIELD_WORD = 1; \
} \
else \
\
if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \
{ \
- target_flags |= MASK_MINIMAL_TOC; \
+ rs6000_isa_flags |= OPTION_MASK_MINIMAL_TOC; \
error ("-mrelocatable and -mno-minimal-toc are incompatible"); \
} \
\
if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \
{ \
- target_flags &= ~MASK_RELOCATABLE; \
+ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
error ("-mrelocatable and -mcall-%s are incompatible", \
rs6000_abi_name); \
} \
\
if (rs6000_current_abi == ABI_AIX && TARGET_LITTLE_ENDIAN) \
{ \
- target_flags &= ~MASK_LITTLE_ENDIAN; \
+ rs6000_isa_flags &= ~OPTION_MASK_LITTLE_ENDIAN; \
error ("-mcall-aixdesc must be big endian"); \
} \
\
/* Treat -fPIC the same as -mrelocatable. */ \
if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \
{ \
- target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \
+ rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \
TARGET_NO_FP_IN_TOC = 1; \
} \
\
#ifndef RS6000_BI_ARCH
# define SUBSUBTARGET_OVERRIDE_OPTIONS \
do { \
- if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT) \
+ if ((TARGET_DEFAULT ^ rs6000_isa_flags) & OPTION_MASK_64BIT) \
error ("-m%s not supported in this configuration", \
- (target_flags & MASK_64BIT) ? "64" : "32"); \
+ (rs6000_isa_flags & OPTION_MASK_64BIT) ? "64" : "32"); \
} while (0)
#endif
#define TARGET_OS_SYSV_CPP_BUILTINS() \
do \
{ \
- if (target_flags_explicit \
- & MASK_RELOCATABLE) \
+ if (rs6000_isa_flags_explicit \
+ & OPTION_MASK_RELOCATABLE) \
builtin_define ("_RELOCATABLE"); \
} \
while (0)
Align to the base type of the bit-field
mstrict-align
-Target Report Mask(STRICT_ALIGN)
+Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
Align to the base type of the bit-field
Don't assume that unaligned accesses are handled by the system
mrelocatable
-Target Report Mask(RELOCATABLE)
+Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags)
Produce code relocatable at runtime
mrelocatable-lib
Produce code relocatable at runtime
mlittle-endian
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code
mlittle
-Target Report RejectNegative Mask(LITTLE_ENDIAN)
+Target Report RejectNegative Mask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce little endian code
mbig-endian
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code
mbig
-Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
+Target Report RejectNegative InverseMask(LITTLE_ENDIAN) Var(rs6000_isa_flags)
Produce big endian code
;; FIXME: This does nothing. What should be done?
no description yet
meabi
-Target Report Mask(EABI)
+Target Report Mask(EABI) Var(rs6000_isa_flags)
Use EABI
mbit-word
no description yet
m64
-Target Report RejectNegative Negative(m32) Mask(64BIT)
+Target Report RejectNegative Negative(m32) Mask(64BIT) Var(rs6000_isa_flags)
Generate 64-bit code
m32
-Target Report RejectNegative Negative(m64) InverseMask(64BIT)
+Target Report RejectNegative Negative(m64) InverseMask(64BIT) Var(rs6000_isa_flags)
Generate 32-bit code
mnewlib
$(OBSTACK_H) $(TREE_H) $(EXPR_H) $(OPTABS_H) except.h function.h \
output.h dbxout.h $(BASIC_BLOCK_H) toplev.h $(GGC_H) $(HASHTAB_H) \
$(TM_P_H) $(TARGET_H) $(TARGET_DEF_H) langhooks.h reload.h gt-rs6000.h \
- cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h
+ cfgloop.h $(OPTS_H) $(COMMON_TARGET_H) dumpfile.h \
+ $(srcdir)/config/rs6000/rs6000-cpus.def
rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \
$(srcdir)/config/rs6000/rs6000-protos.h \
projects / thirdparty / gcc.git / commitdiff
