POWER ISA 3.0 introduces the xssqrtqp instructions, which expects
operands to be in Vector Registers (Altivec/VMX), even though this
instruction belongs to the Vector-Scalar Instruction Set.
In GCC's Extended Assembly for POWER, the 'wq' register constraint is
provided for use with IEEE 754 128-bit floating-point values. However,
this constraint does not limit the register allocation to Vector
Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX)
to the operands of the instruction.
This patch changes the register constraint used in sqrtf128 from 'wq' to
'v', in order to request a Vector Register (Altivec/VMX) for use with
the xssqrtqp instruction.
Tested for powerpc64le and --with-cpu=power9.
[BZ #21941]
* sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
xssqrtqp requires operands to be in Vector Registers
(Altivec/VMX), replace the register constraint 'wq' with 'v'.
* sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
(__ieee754_sqrtf128): Likewise.
+2017-08-10 Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com>
+
+ [BZ #21941]
+ * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
+ xssqrtqp requires operands to be in Vector Registers
+ (Altivec/VMX), replace the register constraint 'wq' with 'v'.
+ * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
+ (__ieee754_sqrtf128): Likewise.
+
2017-08-10 Wilco Dijkstra <wdijkstr@arm.com>
* sysdeps/aarch64/memcmp.S (memcmp):
__ieee754_sqrtf128 (_Float128 __x)
{
_Float128 __z;
- asm ("xssqrtqp %0,%1" : "=wq" (__z) : "wq" (__x));
+ asm ("xssqrtqp %0,%1" : "=v" (__z) : "v" (__x));
return __z;
}
#endif
__ieee754_sqrtf128 (__float128 a)
{
__float128 z;
- asm ("xssqrtqp %0,%1" : "=wq" (z) : "wq" (a));
+ asm ("xssqrtqp %0,%1" : "=v" (z) : "v" (a));
return z;
}
strong_alias (__ieee754_sqrtf128, __sqrtf128_finite)