drm/amd/display: allow dscclk disable

[why]
when dscclk rcg disabled from usr reg option,
dsc clock will remain enabled because driver was doing two things
both dscclk and dsc rcg in the same routine.

Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index b363f5360818d881285c64fb27ed3a01e59ba2e3..6c5d6956612e1b5449a14702c1c969f6b72c2fb2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -1035,6 +1035,7 @@ static void dccg35_enable_dpp_clk_new(
                          DPPCLK0_DTO_MODULO, 0xFF);
 }
 
+
 static void dccg35_disable_dpp_clk_new(
        struct dccg *dccg,
        int inst)
@@ -1771,36 +1772,40 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst)
        //Disable DTO
        switch (inst) {
        case 0:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1);
+
                REG_UPDATE_2(DSCCLK0_DTO_PARAM,
                                DSCCLK0_DTO_PHASE, 0,
                                DSCCLK0_DTO_MODULO, 0);
                REG_UPDATE(DSCCLK_DTO_CTRL,     DSCCLK0_EN, 1);
-               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, 1);
                break;
        case 1:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1);
+
                REG_UPDATE_2(DSCCLK1_DTO_PARAM,
                                DSCCLK1_DTO_PHASE, 0,
                                DSCCLK1_DTO_MODULO, 0);
                REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK1_EN, 1);
-               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, 1);
                break;
        case 2:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1);
+
                REG_UPDATE_2(DSCCLK2_DTO_PARAM,
                                DSCCLK2_DTO_PHASE, 0,
                                DSCCLK2_DTO_MODULO, 0);
                REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK2_EN, 1);
-               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, 1);
                break;
        case 3:
+               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1);
+
                REG_UPDATE_2(DSCCLK3_DTO_PARAM,
                                DSCCLK3_DTO_PHASE, 0,
                                DSCCLK3_DTO_MODULO, 0);
                REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK3_EN, 1);
-               if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
-                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, 1);
                break;
        default:
                BREAK_TO_DEBUGGER();
@@ -1813,9 +1818,6 @@ static void dccg35_disable_dscclk(struct dccg *dccg,
 {
        struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
-       if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
-               return;
-
        switch (inst) {
        case 0:
                REG_UPDATE(DSCCLK_DTO_CTRL, DSCCLK0_EN, 0);