drm/i915: Set PKG_C_LATENCY.added_wake_time to 0

AFAIK PKG_C_LATENCY.added_wake_time only matters for flip queue.
As long as we're not using that there's no point in adding any
extra wake time.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250624170049.27284-2-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f234a3aa3d15b3a75641abce61c4a606d8c97a87..855bbce889c84cc5feca4d84752b7823fc64fd88 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -33,12 +33,6 @@
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 
-/*It is expected that DSB can do posted writes to every register in
- * the pipe and planes within 100us. For flip queue use case, the
- * recommended DSB execution time is 100us + one SAGV block time.
- */
-#define DSB_EXE_TIME 100
-
 struct intel_dbuf_state {
        struct intel_global_state base;
 
@@ -2899,9 +2893,6 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
        }
 
        if (fixed_refresh_rate) {
-               added_wake_time = DSB_EXE_TIME +
-                       display->sagv.block_time_us;
-
                latency = skl_watermark_max_latency(display, 1);
 
                /* Wa_22020432604 */