int32_t k = 0;
if (as->flagmcp == as->mcp) { /* Drop test r,r instruction. */
as->flagmcp = NULL;
- as->mcp += (LJ_64 && *as->mcp != XI_TEST) ? 3 : 2;
+ as->mcp += (LJ_64 && *as->mcp < XI_TESTb) ? 3 : 2;
}
right = IR(rref)->r;
if (ra_hasreg(right)) {
asm_guardcc(as, cc);
if (usetest && left != RID_MRM) {
/* Use test r,r instead of cmp r,0. */
- emit_rr(as, XO_TEST, r64 + left, left);
+ emit_rr(as, irt_isu8(ir->t) ? XO_TESTb : XO_TEST, r64 + left, left);
if (irl+1 == ir) /* Referencing previous ins? */
as->flagmcp = as->mcp; /* Set flag to drop test r,r if possible. */
} else {
tr = TREF_NIL;
} else {
crec_snap_caller(J);
+#if LJ_TARGET_X86ORX64
+ /* Note: only the x86/x64 backend supports U8 and only for EQ(tr, 0). */
+ lj_ir_set(J, IRTG(IR_NE, IRT_U8), tr, lj_ir_kint(J, 0));
+#else
lj_ir_set(J, IRTGI(IR_NE), tr, lj_ir_kint(J, 0));
+#endif
J->postproc = LJ_POST_FIXGUARDSNAP;
tr = TREF_TRUE;
}