--- /dev/null
+From 0b61993367fa1d590b83f6247d84edc10e0af96d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 28 Oct 2019 11:58:03 +0100
+Subject: ALSA: hda - Fix pending unsol events at shutdown
+
+From: Takashi Iwai <tiwai@suse.de>
+
+[ Upstream commit ca58f55108fee41d87c9123f85ad4863e5de7f45 ]
+
+This is an alternative fix attemp for the issue reported in the commit
+caa8422d01e9 ("ALSA: hda: Flush interrupts on disabling") that was
+reverted later due to regressions. Instead of tweaking the hardware
+disablement order and the enforced irq flushing, do calling
+cancel_work_sync() of the unsol work early enough, and explicitly
+ignore the unsol events during the shutdown by checking the
+bus->shutdown flag.
+
+Fixes: caa8422d01e9 ("ALSA: hda: Flush interrupts on disabling")
+Cc: Chris Wilson <chris@chris-wilson.co.uk>
+Link: https://lore.kernel.org/r/s5h1ruxt9cz.wl-tiwai@suse.de
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/hda_bind.c | 4 ++++
+ sound/pci/hda/hda_intel.c | 3 +++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/sound/pci/hda/hda_bind.c b/sound/pci/hda/hda_bind.c
+index 8272b50b83493..6a85645663759 100644
+--- a/sound/pci/hda/hda_bind.c
++++ b/sound/pci/hda/hda_bind.c
+@@ -43,6 +43,10 @@ static void hda_codec_unsol_event(struct hdac_device *dev, unsigned int ev)
+ {
+ struct hda_codec *codec = container_of(dev, struct hda_codec, core);
+
++ /* ignore unsol events during shutdown */
++ if (codec->bus->shutdown)
++ return;
++
+ if (codec->patch_ops.unsol_event)
+ codec->patch_ops.unsol_event(codec, ev);
+ }
+diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
+index 46c2b1022495f..c2740366815d6 100644
+--- a/sound/pci/hda/hda_intel.c
++++ b/sound/pci/hda/hda_intel.c
+@@ -1383,8 +1383,11 @@ static int azx_free(struct azx *chip)
+ static int azx_dev_disconnect(struct snd_device *device)
+ {
+ struct azx *chip = device->device_data;
++ struct hdac_bus *bus = azx_bus(chip);
+
+ chip->bus.shutdown = 1;
++ cancel_work_sync(&bus->unsol_work);
++
+ return 0;
+ }
+
+--
+2.20.1
+
--- /dev/null
+From 31e2c4b00db0d227c6c50625294c10cd78e0594b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 11 Nov 2019 15:38:38 +0200
+Subject: ALSA: hda: hdmi - fix pin setup on Tigerlake
+
+From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
+
+[ Upstream commit a7d0358ea3b7f8d7216e663c1ae71cabf7ac24e3 ]
+
+Apply same logic to pin setup as on previous platforms. Fixes
+errors in HDMI/DP playback.
+
+Tested with both snd-hda-intel and SOF drivers.
+
+Fixes: 9a11ba7388f1 ("ALSA: hda: hdmi - add Tigerlake support")
+Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
+Link: https://lore.kernel.org/r/20191111133838.21213-1-kai.vehmanen@linux.intel.com
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/pci/hda/patch_hdmi.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c
+index ff99f5feaace9..a4ad81d088e81 100644
+--- a/sound/pci/hda/patch_hdmi.c
++++ b/sound/pci/hda/patch_hdmi.c
+@@ -45,10 +45,12 @@ MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
+ ((codec)->core.vendor_id == 0x80862800))
+ #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
+ #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
++#define is_tigerlake(codec) ((codec)->core.vendor_id == 0x80862812)
+ #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
+ || is_skylake(codec) || is_broxton(codec) \
+ || is_kabylake(codec) || is_geminilake(codec) \
+- || is_cannonlake(codec) || is_icelake(codec))
++ || is_cannonlake(codec) || is_icelake(codec) \
++ || is_tigerlake(codec))
+ #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
+ #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
+ #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
+--
+2.20.1
+
--- /dev/null
+From 30ed4e7cc193f666f61f1cc0cec48b93fc57d4cf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Oct 2019 16:33:19 +0800
+Subject: cpufreq: imx-cpufreq-dt: Correct i.MX8MN's default speed grade value
+
+From: Anson Huang <Anson.Huang@nxp.com>
+
+[ Upstream commit af44d180e3de4cb411ce327b147ea3513f0bbbcb ]
+
+i.MX8MN has different speed grade definition compared to
+i.MX8MQ/i.MX8MM, when fuses are NOT written, the default
+speed_grade should be set to minimum available OPP defined
+in DT which is 1.2GHz, the corresponding speed_grade value
+should be 0xb.
+
+Fixes: 5b8010ba70d5 ("cpufreq: imx-cpufreq-dt: Add i.MX8MN support")
+Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/cpufreq/imx-cpufreq-dt.c | 20 ++++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
+index 35db14cf31026..85a6efd6b68f9 100644
+--- a/drivers/cpufreq/imx-cpufreq-dt.c
++++ b/drivers/cpufreq/imx-cpufreq-dt.c
+@@ -44,19 +44,19 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
+ mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
+
+ /*
+- * Early samples without fuses written report "0 0" which means
+- * consumer segment and minimum speed grading.
+- *
+- * According to datasheet minimum speed grading is not supported for
+- * consumer parts so clamp to 1 to avoid warning for "no OPPs"
++ * Early samples without fuses written report "0 0" which may NOT
++ * match any OPP defined in DT. So clamp to minimum OPP defined in
++ * DT to avoid warning for "no OPPs".
+ *
+ * Applies to i.MX8M series SoCs.
+ */
+- if (mkt_segment == 0 && speed_grade == 0 && (
+- of_machine_is_compatible("fsl,imx8mm") ||
+- of_machine_is_compatible("fsl,imx8mn") ||
+- of_machine_is_compatible("fsl,imx8mq")))
+- speed_grade = 1;
++ if (mkt_segment == 0 && speed_grade == 0) {
++ if (of_machine_is_compatible("fsl,imx8mm") ||
++ of_machine_is_compatible("fsl,imx8mq"))
++ speed_grade = 1;
++ if (of_machine_is_compatible("fsl,imx8mn"))
++ speed_grade = 0xb;
++ }
+
+ supported_hw[0] = BIT(speed_grade);
+ supported_hw[1] = BIT(mkt_segment);
+--
+2.20.1
+
--- /dev/null
+From ec9833435eeaa6b1b7a34c91b8479aa8a5bd432c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 22 Aug 2019 23:15:18 +0200
+Subject: drm/mcde: Fix an error handling path in 'mcde_probe()'
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 15c665bb4637310bc8ce5f357b6a6e5a8aafc7c1 ]
+
+If we don't find any matching components, we should go through the error
+handling path, in order to free some resources.
+
+Fixes: ca5be902a87d ("drm/mcde: Fix uninitialized variable")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20190822211518.5578-1-christophe.jaillet@wanadoo.fr
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/mcde/mcde_drv.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/mcde/mcde_drv.c b/drivers/gpu/drm/mcde/mcde_drv.c
+index a810568c76df7..1bd744231aada 100644
+--- a/drivers/gpu/drm/mcde/mcde_drv.c
++++ b/drivers/gpu/drm/mcde/mcde_drv.c
+@@ -487,7 +487,8 @@ static int mcde_probe(struct platform_device *pdev)
+ }
+ if (!match) {
+ dev_err(dev, "no matching components\n");
+- return -ENODEV;
++ ret = -ENODEV;
++ goto clk_disable;
+ }
+ if (IS_ERR(match)) {
+ dev_err(dev, "could not create component match\n");
+--
+2.20.1
+
--- /dev/null
+From 3888c4f2f6d49cf20837a68a6b4055b4779d4a65 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Nov 2019 20:07:51 +0000
+Subject: EDAC/ghes: Fix locking and memory barrier issues
+
+From: Robert Richter <rrichter@marvell.com>
+
+[ Upstream commit 23f61b9fc5cc10d87f66e50518707eec2a0fbda1 ]
+
+The ghes registration and refcount is broken in several ways:
+
+ * ghes_edac_register() returns with success for a 2nd instance
+ even if a first instance's registration is still running. This is
+ not correct as the first instance may fail later. A subsequent
+ registration may not finish before the first. Parallel registrations
+ must be avoided.
+
+ * The refcount was increased even if a registration failed. This
+ leads to stale counters preventing the device from being released.
+
+ * The ghes refcount may not be decremented properly on unregistration.
+ Always decrement the refcount once ghes_edac_unregister() is called to
+ keep the refcount sane.
+
+ * The ghes_pvt pointer is handed to the irq handler before registration
+ finished.
+
+ * The mci structure could be freed while the irq handler is running.
+
+Fix this by adding a mutex to ghes_edac_register(). This mutex
+serializes instances to register and unregister. The refcount is only
+increased if the registration succeeded. This makes sure the refcount is
+in a consistent state after registering or unregistering a device.
+
+Note: A spinlock cannot be used here as the code section may sleep.
+
+The ghes_pvt is protected by ghes_lock now. This ensures the pointer is
+not updated before registration was finished or while the irq handler is
+running. It is unset before unregistering the device including necessary
+(implicit) memory barriers making the changes visible to other CPUs.
+Thus, the device can not be used anymore by an interrupt.
+
+Also, rename ghes_init to ghes_refcount for better readability and
+switch to refcount API.
+
+A refcount is needed because there can be multiple GHES structures being
+defined (see ACPI 6.3 specification, 18.3.2.7 Generic Hardware Error
+Source, "Some platforms may describe multiple Generic Hardware Error
+Source structures with different notification types, ...").
+
+Another approach to use the mci's device refcount (get_device()) and
+have a release function does not work here. A release function will be
+called only for device_release() with the last put_device() call. The
+device must be deleted *before* that with device_del(). This is only
+possible by maintaining an own refcount.
+
+ [ bp: touchups. ]
+
+Fixes: 0fe5f281f749 ("EDAC, ghes: Model a single, logical memory controller")
+Fixes: 1e72e673b9d1 ("EDAC/ghes: Fix Use after free in ghes_edac remove path")
+Co-developed-by: James Morse <james.morse@arm.com>
+Signed-off-by: James Morse <james.morse@arm.com>
+Co-developed-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Robert Richter <rrichter@marvell.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
+Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
+Cc: Tony Luck <tony.luck@intel.com>
+Link: https://lkml.kernel.org/r/20191105200732.3053-1-rrichter@marvell.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/edac/ghes_edac.c | 90 +++++++++++++++++++++++++++++-----------
+ 1 file changed, 66 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/edac/ghes_edac.c b/drivers/edac/ghes_edac.c
+index 2059e43ccc01a..1163c382d4a55 100644
+--- a/drivers/edac/ghes_edac.c
++++ b/drivers/edac/ghes_edac.c
+@@ -26,9 +26,18 @@ struct ghes_edac_pvt {
+ char msg[80];
+ };
+
+-static atomic_t ghes_init = ATOMIC_INIT(0);
++static refcount_t ghes_refcount = REFCOUNT_INIT(0);
++
++/*
++ * Access to ghes_pvt must be protected by ghes_lock. The spinlock
++ * also provides the necessary (implicit) memory barrier for the SMP
++ * case to make the pointer visible on another CPU.
++ */
+ static struct ghes_edac_pvt *ghes_pvt;
+
++/* GHES registration mutex */
++static DEFINE_MUTEX(ghes_reg_mutex);
++
+ /*
+ * Sync with other, potentially concurrent callers of
+ * ghes_edac_report_mem_error(). We don't know what the
+@@ -79,9 +88,8 @@ static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
+ (*num_dimm)++;
+ }
+
+-static int get_dimm_smbios_index(u16 handle)
++static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle)
+ {
+- struct mem_ctl_info *mci = ghes_pvt->mci;
+ int i;
+
+ for (i = 0; i < mci->tot_dimms; i++) {
+@@ -198,14 +206,11 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
+ enum hw_event_mc_err_type type;
+ struct edac_raw_error_desc *e;
+ struct mem_ctl_info *mci;
+- struct ghes_edac_pvt *pvt = ghes_pvt;
++ struct ghes_edac_pvt *pvt;
+ unsigned long flags;
+ char *p;
+ u8 grain_bits;
+
+- if (!pvt)
+- return;
+-
+ /*
+ * We can do the locking below because GHES defers error processing
+ * from NMI to IRQ context. Whenever that changes, we'd at least
+@@ -216,6 +221,10 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
+
+ spin_lock_irqsave(&ghes_lock, flags);
+
++ pvt = ghes_pvt;
++ if (!pvt)
++ goto unlock;
++
+ mci = pvt->mci;
+ e = &mci->error_desc;
+
+@@ -348,7 +357,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
+ p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
+ mem_err->mem_dev_handle);
+
+- index = get_dimm_smbios_index(mem_err->mem_dev_handle);
++ index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle);
+ if (index >= 0) {
+ e->top_layer = index;
+ e->enable_per_layer_report = true;
+@@ -443,6 +452,8 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
+ grain_bits, e->syndrome, pvt->detail_location);
+
+ edac_raw_mc_handle_error(type, mci, e);
++
++unlock:
+ spin_unlock_irqrestore(&ghes_lock, flags);
+ }
+
+@@ -457,10 +468,12 @@ static struct acpi_platform_list plat_list[] = {
+ int ghes_edac_register(struct ghes *ghes, struct device *dev)
+ {
+ bool fake = false;
+- int rc, num_dimm = 0;
++ int rc = 0, num_dimm = 0;
+ struct mem_ctl_info *mci;
++ struct ghes_edac_pvt *pvt;
+ struct edac_mc_layer layers[1];
+ struct ghes_edac_dimm_fill dimm_fill;
++ unsigned long flags;
+ int idx = -1;
+
+ if (IS_ENABLED(CONFIG_X86)) {
+@@ -472,11 +485,14 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
+ idx = 0;
+ }
+
++ /* finish another registration/unregistration instance first */
++ mutex_lock(&ghes_reg_mutex);
++
+ /*
+ * We have only one logical memory controller to which all DIMMs belong.
+ */
+- if (atomic_inc_return(&ghes_init) > 1)
+- return 0;
++ if (refcount_inc_not_zero(&ghes_refcount))
++ goto unlock;
+
+ /* Get the number of DIMMs */
+ dmi_walk(ghes_edac_count_dimms, &num_dimm);
+@@ -494,12 +510,13 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
+ if (!mci) {
+ pr_info("Can't allocate memory for EDAC data\n");
+- return -ENOMEM;
++ rc = -ENOMEM;
++ goto unlock;
+ }
+
+- ghes_pvt = mci->pvt_info;
+- ghes_pvt->ghes = ghes;
+- ghes_pvt->mci = mci;
++ pvt = mci->pvt_info;
++ pvt->ghes = ghes;
++ pvt->mci = mci;
+
+ mci->pdev = dev;
+ mci->mtype_cap = MEM_FLAG_EMPTY;
+@@ -541,23 +558,48 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
+ if (rc < 0) {
+ pr_info("Can't register at EDAC core\n");
+ edac_mc_free(mci);
+- return -ENODEV;
++ rc = -ENODEV;
++ goto unlock;
+ }
+- return 0;
++
++ spin_lock_irqsave(&ghes_lock, flags);
++ ghes_pvt = pvt;
++ spin_unlock_irqrestore(&ghes_lock, flags);
++
++ /* only increment on success */
++ refcount_inc(&ghes_refcount);
++
++unlock:
++ mutex_unlock(&ghes_reg_mutex);
++
++ return rc;
+ }
+
+ void ghes_edac_unregister(struct ghes *ghes)
+ {
+ struct mem_ctl_info *mci;
++ unsigned long flags;
+
+- if (!ghes_pvt)
+- return;
++ mutex_lock(&ghes_reg_mutex);
+
+- if (atomic_dec_return(&ghes_init))
+- return;
++ if (!refcount_dec_and_test(&ghes_refcount))
++ goto unlock;
+
+- mci = ghes_pvt->mci;
++ /*
++ * Wait for the irq handler being finished.
++ */
++ spin_lock_irqsave(&ghes_lock, flags);
++ mci = ghes_pvt ? ghes_pvt->mci : NULL;
+ ghes_pvt = NULL;
+- edac_mc_del_mc(mci->pdev);
+- edac_mc_free(mci);
++ spin_unlock_irqrestore(&ghes_lock, flags);
++
++ if (!mci)
++ goto unlock;
++
++ mci = edac_mc_del_mc(mci->pdev);
++ if (mci)
++ edac_mc_free(mci);
++
++unlock:
++ mutex_unlock(&ghes_reg_mutex);
+ }
+--
+2.20.1
+
--- /dev/null
+From 56ac79590d0d05b8d575a61e57273bdcf6224ef9 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 22 Oct 2019 13:27:17 +0000
+Subject: kselftest: Fix NULL INSTALL_PATH for TARGETS runlist
+
+From: Prabhakar Kushwaha <pkushwaha@marvell.com>
+
+[ Upstream commit 02bf1f8b3c43eec5053c35c14fb9f138186b4123 ]
+
+As per commit 131b30c94fbc ("kselftest: exclude failed TARGETS from
+runlist") failed targets were excluded from the runlist. But value
+$$INSTALL_PATH is always NULL. It should be $INSTALL_PATH instead
+$$INSTALL_PATH.
+
+So, fix Makefile to use $INSTALL_PATH.
+
+Fixes: 131b30c94fbc ("kselftest: exclude failed TARGETS from runlist")
+Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
+Reviewed-by: Cristian Marussi <cristian.marussi@arm.com>
+Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile
+index 1779923d7a7b8..3e5474110dfd3 100644
+--- a/tools/testing/selftests/Makefile
++++ b/tools/testing/selftests/Makefile
+@@ -203,7 +203,7 @@ ifdef INSTALL_PATH
+ @# included in the generated runlist.
+ for TARGET in $(TARGETS); do \
+ BUILD_TARGET=$$BUILD/$$TARGET; \
+- [ ! -d $$INSTALL_PATH/$$TARGET ] && echo "Skipping non-existent dir: $$TARGET" && continue; \
++ [ ! -d $(INSTALL_PATH)/$$TARGET ] && echo "Skipping non-existent dir: $$TARGET" && continue; \
+ echo "[ -w /dev/kmsg ] && echo \"kselftest: Running tests in $$TARGET\" >> /dev/kmsg" >> $(ALL_SCRIPT); \
+ echo "cd $$TARGET" >> $(ALL_SCRIPT); \
+ echo -n "run_many" >> $(ALL_SCRIPT); \
+--
+2.20.1
+
--- /dev/null
+From 42283d2ed501ad0c3aeebddf3e4b6c4f7978e32c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 21 Sep 2019 09:00:31 +0300
+Subject: md/raid0: Fix an error message in raid0_make_request()
+
+From: Dan Carpenter <dan.carpenter@oracle.com>
+
+[ Upstream commit e3fc3f3d0943b126f76b8533960e4168412d9e5a ]
+
+The first argument to WARN() is supposed to be a condition. The
+original code will just print the mdname() instead of the full warning
+message.
+
+Fixes: c84a1372df92 ("md/raid0: avoid RAID0 data corruption due to layout confusion.")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Song Liu <songliubraving@fb.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/md/raid0.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c
+index c3445d2cedb9d..94c3f1a6fb5c9 100644
+--- a/drivers/md/raid0.c
++++ b/drivers/md/raid0.c
+@@ -612,7 +612,7 @@ static bool raid0_make_request(struct mddev *mddev, struct bio *bio)
+ tmp_dev = map_sector(mddev, zone, sector, §or);
+ break;
+ default:
+- WARN("md/raid0:%s: Invalid layout\n", mdname(mddev));
++ WARN(1, "md/raid0:%s: Invalid layout\n", mdname(mddev));
+ bio_io_error(bio);
+ return true;
+ }
+--
+2.20.1
+
--- /dev/null
+From 0755a3f5971b852226dbeb6ed9dfd2ef06d6fe53 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 27 Nov 2019 11:56:31 +0200
+Subject: perf script: Fix invalid LBR/binary mismatch error
+
+From: Adrian Hunter <adrian.hunter@intel.com>
+
+[ Upstream commit 5172672da02e483d9b3c4d814c3482d0c8ffb1a6 ]
+
+The 'len' returned by grab_bb() includes an extra MAXINSN bytes to allow
+for the last instruction, so the the final 'offs' will not be 'len'.
+Fix the error condition logic accordingly.
+
+Before:
+
+ $ perf record -e '{intel_pt//,cpu/mem_inst_retired.all_loads,aux-sample-size=8192/pp}:u' grep -rqs jhgjhg /boot
+ [ perf record: Woken up 19 times to write data ]
+ [ perf record: Captured and wrote 2.274 MB perf.data ]
+ $ perf script -F +brstackinsn --xed --itrace=i1usl100 | head
+ grep 13759 [002] 8091.310257: 1862 instructions:uH: 5641d58069eb bmexec+0x86b (/bin/grep)
+ bmexec+2485:
+ 00005641d5806b35 jnz 0x5641d5806bd0 # MISPRED
+ 00005641d5806bd0 movzxb (%r13,%rdx,1), %eax
+ 00005641d5806bd6 add %rdi, %rax
+ 00005641d5806bd9 movzxb -0x1(%rax), %edx
+ 00005641d5806bdd cmp %rax, %r14
+ 00005641d5806be0 jnb 0x5641d58069c0 # MISPRED
+ mismatch of LBR data and executable
+ 00005641d58069c0 movzxb (%r13,%rdx,1), %edi
+
+After:
+
+ $ perf script -F +brstackinsn --xed --itrace=i1usl100 | head
+ grep 13759 [002] 8091.310257: 1862 instructions:uH: 5641d58069eb bmexec+0x86b (/bin/grep)
+ bmexec+2485:
+ 00005641d5806b35 jnz 0x5641d5806bd0 # MISPRED
+ 00005641d5806bd0 movzxb (%r13,%rdx,1), %eax
+ 00005641d5806bd6 add %rdi, %rax
+ 00005641d5806bd9 movzxb -0x1(%rax), %edx
+ 00005641d5806bdd cmp %rax, %r14
+ 00005641d5806be0 jnb 0x5641d58069c0 # MISPRED
+ 00005641d58069c0 movzxb (%r13,%rdx,1), %edi
+ 00005641d58069c6 add %rax, %rdi
+
+Fixes: e98df280bc2a ("perf script brstackinsn: Fix recovery from LBR/binary mismatch")
+Reported-by: Andi Kleen <ak@linux.intel.com>
+Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
+Cc: Jiri Olsa <jolsa@redhat.com>
+Link: http://lore.kernel.org/lkml/20191127095631.15663-1-adrian.hunter@intel.com
+Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/perf/builtin-script.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c
+index c14a1cdad80c0..b0de5684ebd61 100644
+--- a/tools/perf/builtin-script.c
++++ b/tools/perf/builtin-script.c
+@@ -1075,7 +1075,7 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample,
+ insn++;
+ }
+ }
+- if (off != (unsigned)len)
++ if (off != end - start)
+ printed += fprintf(fp, "\tmismatch of LBR data and executable\n");
+ }
+
+--
+2.20.1
+
binder-fix-race-between-mmap-and-binder_alloc_print_pages.patch
binder-prevent-repeated-use-of-mmap-via-null-mapping.patch
binder-handle-start-null-in-binder_update_page_range.patch
+alsa-hda-fix-pending-unsol-events-at-shutdown.patch
+cpufreq-imx-cpufreq-dt-correct-i.mx8mn-s-default-spe.patch
+md-raid0-fix-an-error-message-in-raid0_make_request.patch
+drm-mcde-fix-an-error-handling-path-in-mcde_probe.patch
+watchdog-aspeed-fix-clock-behaviour-for-ast2600.patch
+edac-ghes-fix-locking-and-memory-barrier-issues.patch
+perf-script-fix-invalid-lbr-binary-mismatch-error.patch
+kselftest-fix-null-install_path-for-targets-runlist.patch
+alsa-hda-hdmi-fix-pin-setup-on-tigerlake.patch
--- /dev/null
+From 061df8edc8d67094fb4047ce497c96ea85394fd2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 8 Nov 2019 13:59:05 +1030
+Subject: watchdog: aspeed: Fix clock behaviour for ast2600
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Joel Stanley <joel@jms.id.au>
+
+[ Upstream commit c04571251b3d842096f1597f5d4badb508be016d ]
+
+The ast2600 no longer uses bit 4 in the control register to indicate a
+1MHz clock (It now controls whether this watchdog is reset by a SOC
+reset). This means we do not want to set it. It also does not need to be
+set for the ast2500, as it is read-only on that SoC.
+
+The comment next to the clock rate selection wandered away from where it
+was set, so put it back next to the register setting it's describing.
+
+Fixes: b3528b487448 ("watchdog: aspeed: Add support for AST2600")
+Signed-off-by: Joel Stanley <joel@jms.id.au>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/20191108032905.22463-1-joel@jms.id.au
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/watchdog/aspeed_wdt.c | 16 ++++++++++------
+ 1 file changed, 10 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
+index 5b64bc2e87888..c59e981841e19 100644
+--- a/drivers/watchdog/aspeed_wdt.c
++++ b/drivers/watchdog/aspeed_wdt.c
+@@ -202,11 +202,6 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
+ if (IS_ERR(wdt->base))
+ return PTR_ERR(wdt->base);
+
+- /*
+- * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
+- * runs at 1MHz. We chose to always run at 1MHz, as there's no
+- * good reason to have a faster watchdog counter.
+- */
+ wdt->wdd.info = &aspeed_wdt_info;
+ wdt->wdd.ops = &aspeed_wdt_ops;
+ wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
+@@ -222,7 +217,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
+ return -EINVAL;
+ config = ofdid->data;
+
+- wdt->ctrl = WDT_CTRL_1MHZ_CLK;
++ /*
++ * On clock rates:
++ * - ast2400 wdt can run at PCLK, or 1MHz
++ * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
++ * - ast2600 always runs at 1MHz
++ *
++ * Set the ast2400 to run at 1MHz as it simplifies the driver.
++ */
++ if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
++ wdt->ctrl = WDT_CTRL_1MHZ_CLK;
+
+ /*
+ * Control reset on a per-device basis to ensure the
+--
+2.20.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
