RISC-V: Add available vector size for RVV

For RVV, we have VLS modes enable according to TARGET_MIN_VLEN
from M1 to M8.

For example, when TARGET_MIN_VLEN = 128 bits, we enable
128/256/512/1024 bits VLS modes.

This patch fixes following FAIL:
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects  scan-tree-dump-times slp2 "optimized: basic block" 2
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 2

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add 256/512/1024

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index af52c38433d6a8302ff140a3d95326381c7d96ab..dc366d35a0a1e502357f930335ec55ab329bdb08 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -8881,7 +8881,7 @@ proc available_vector_sizes { } {
        lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
     } elseif { [istarget riscv*-*-*] } {
        if { [check_effective_target_riscv_v] } {
-           lappend result 0 32 64 128
+           lappend result 0 32 64 128 256 512 1024
        }
        lappend result 128
     } else {