clk: renesas: r9a09g057: Add USB3.0 clocks/resets

Add USB3.0 clock and reset entries.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251101050034.738807-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index c9f6d91884c39b404aab353beb5f7dca893ddea2..400d9e94f2e9f338be4eb5d2dee9e4848295a13d 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -17,7 +17,7 @@
 
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
-       LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,
+       LAST_DT_CORE_CLK = R9A09G057_USB3_1_CLKCORE,
 
        /* External Input Clocks */
        CLK_AUDIO_EXTAL,
@@ -235,6 +235,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
                  CLK_PLLETH_DIV_125_FIX, 1, 1),
        DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
                             FIXED_MOD_CONF_XSPI),
+       DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G057_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("usb3_0_core_clk", R9A09G057_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("usb3_1_ref_alt_clk_p", R9A09G057_USB3_1_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
+       DEF_FIXED("usb3_1_core_clk", R9A09G057_USB3_1_CLKCORE, CLK_QEXTAL, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -360,6 +364,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(8, BIT(4))),
        DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
                                                BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("usb3_0_aclk",                  CLK_PLLDTY_DIV8, 10, 15, 5, 15,
+                                               BUS_MSTOP(7, BIT(12))),
+       DEF_MOD("usb3_0_pclk_usbtst",           CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
+                                               BUS_MSTOP(7, BIT(14))),
+       DEF_MOD("usb3_1_aclk",                  CLK_PLLDTY_DIV8, 11, 1, 5, 17,
+                                               BUS_MSTOP(7, BIT(13))),
+       DEF_MOD("usb3_1_pclk_usbtst",           CLK_PLLDTY_ACPU_DIV4, 11, 2, 5, 18,
+                                               BUS_MSTOP(7, BIT(15))),
        DEF_MOD("usb2_0_u2h0_hclk",             CLK_PLLDTY_DIV8, 11, 3, 5, 19,
                                                BUS_MSTOP(7, BIT(7))),
        DEF_MOD("usb2_0_u2h1_hclk",             CLK_PLLDTY_DIV8, 11, 4, 5, 20,
@@ -501,6 +513,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
+       DEF_RST(10, 10, 4, 27),         /* USB3_0_ARESETN */
+       DEF_RST(10, 11, 4, 28),         /* USB3_1_ARESETN */
        DEF_RST(10, 12, 4, 29),         /* USB2_0_U2H0_HRESETN */
        DEF_RST(10, 13, 4, 30),         /* USB2_0_U2H1_HRESETN */
        DEF_RST(10, 14, 4, 31),         /* USB2_0_U2P_EXL_SYSRST */