KVM: arm64: nv: Honor MDCR_EL2.{TPM, TPMCR} in Host EL0

TPM and TPMCR trap bits also affect Host EL0. How fun.

Mark these two trap bits as such and take advantage of the new
infrastructure for dealing w/ EL0 traps.

Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241025182354.3364124-10-oliver.upton@linux.dev
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index b072098ee44ec33e23225673c53210f48dd13a6d..4f14fa47df8e9a9dadd37edbaf25028ac4d47068 100644 (file)
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -304,13 +304,15 @@ static const struct trap_bits coarse_trap_bits[] = {
                .index          = MDCR_EL2,
                .value          = MDCR_EL2_TPMCR,
                .mask           = MDCR_EL2_TPMCR,
-               .behaviour      = BEHAVE_FORWARD_RW,
+               .behaviour      = BEHAVE_FORWARD_RW |
+                                 BEHAVE_FORWARD_IN_HOST_EL0,
        },
        [CGT_MDCR_TPM] = {
                .index          = MDCR_EL2,
                .value          = MDCR_EL2_TPM,
                .mask           = MDCR_EL2_TPM,
-               .behaviour      = BEHAVE_FORWARD_RW,
+               .behaviour      = BEHAVE_FORWARD_RW |
+                                 BEHAVE_FORWARD_IN_HOST_EL0,
        },
        [CGT_MDCR_TDE] = {
                .index          = MDCR_EL2,