--- /dev/null
+From 2af250ed9d08e11b5e900672042ac0960f36b0da Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 23 Apr 2020 17:09:21 -0400
+Subject: drm/msm/a6xx: update a6xx_hw_init for A640 and A650
+
+From: Jonathan Marek <jonathan@marek.ca>
+
+[ Upstream commit 24e6938ec604b7dc0306c972c1aa029ff03bb36a ]
+
+Adreno 640 and 650 GPUs need some registers set differently.
+
+Signed-off-by: Jonathan Marek <jonathan@marek.ca>
+Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++++++
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 55 ++++++++++++++++++++++-----
+ 2 files changed, 60 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+index f44553ec31935..9121aceb0f97c 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
++++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+@@ -1047,6 +1047,8 @@ enum a6xx_tex_type {
+
+ #define REG_A6XX_CP_MISC_CNTL 0x00000840
+
++#define REG_A6XX_CP_APRIV_CNTL 0x00000844
++
+ #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
+
+ #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
+@@ -1764,6 +1766,8 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
+
+ #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
+
++#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
++
+ #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
+
+ #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
+@@ -2418,6 +2422,16 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
+
+ #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
+
++#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
++
++#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
++
++#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
++
++#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
++
++#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
++
+ #define REG_A6XX_TPL1_PERFCTR_TP_SEL_0 0x0000b610
+
+ #define REG_A6XX_TPL1_PERFCTR_TP_SEL_1 0x0000b611
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+index be68d4e6551c2..c3a81594f4fb7 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+@@ -411,7 +411,16 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+
+ /* VBIF start */
+ gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
+- gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
++ if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
++ gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
++ gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
++ gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
++ gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
++ gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
++ gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
++ } else {
++ gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
++ }
+
+ /* Make all blocks contribute to the GPU BUSY perf counter */
+ gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
+@@ -424,25 +433,35 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+ gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
+ gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
+
+- /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
+- gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
+- REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
++ if (!adreno_is_a650(adreno_gpu)) {
++ /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
++ gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
++ REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
+
+- gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
+- REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
+- 0x00100000 + adreno_gpu->gmem - 1);
++ gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
++ REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
++ 0x00100000 + adreno_gpu->gmem - 1);
++ }
+
+ gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
+ gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
+
+- gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
++ if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
++ gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
++ else
++ gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
+ gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
+
+ /* Setting the mem pool size */
+ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
+
+ /* Setting the primFifo thresholds default values */
+- gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
++ if (adreno_is_a650(adreno_gpu))
++ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
++ else if (adreno_is_a640(adreno_gpu))
++ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
++ else
++ gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
+
+ /* Set the AHB default slave response to "ERROR" */
+ gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
+@@ -464,6 +483,19 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+
+ gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
+
++ /* Set weights for bicubic filtering */
++ if (adreno_is_a650(adreno_gpu)) {
++ gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
++ gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
++ 0x3fe05ff4);
++ gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
++ 0x3fa0ebee);
++ gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
++ 0x3f5193ed);
++ gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
++ 0x3f0243f0);
++ }
++
+ /* Protect registers from the CP */
+ gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
+
+@@ -501,6 +533,11 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+ A6XX_PROTECT_RDONLY(0x980, 0x4));
+ gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
+
++ if (adreno_is_a650(adreno_gpu)) {
++ gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
++ (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
++ }
++
+ /* Enable interrupts */
+ gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
+
+--
+2.25.1
+
--- /dev/null
+From 543cdf4afdb846ccab5eb34f191cefa39e4cc2f2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 3 Sep 2020 20:03:13 -0600
+Subject: drm/msm: Disable the RPTR shadow
+
+From: Jordan Crouse <jcrouse@codeaurora.org>
+
+[ Upstream commit f6828e0c4045f03f9cf2df6c2a768102641183f4 ]
+
+Disable the RPTR shadow across all targets. It will be selectively
+re-enabled later for targets that need it.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 5 +++++
+ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 10 +++++++++
+ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 10 +++++++++
+ drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 ++++++++--
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++++
+ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 27 ++-----------------------
+ 6 files changed, 43 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+index 1f83bc18d5008..80f3b1da9fc26 100644
+--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+@@ -164,6 +164,11 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
+ if (ret)
+ return ret;
+
++ gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
++ MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
++
++ gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
++
+ /* NOTE: PM4/micro-engine firmware registers look to be the same
+ * for a2xx and a3xx.. we could possibly push that part down to
+ * adreno_gpu base class. Or push both PM4 and PFP but
+diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+index 5f7e98028eaf4..eeba2deeca1e8 100644
+--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+@@ -215,6 +215,16 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
+ if (ret)
+ return ret;
+
++ /*
++ * Use the default ringbuffer size and block size but disable the RPTR
++ * shadow
++ */
++ gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
++ MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
++
++ /* Set the ringbuffer address */
++ gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
++
+ /* setup access protection: */
+ gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
+
+diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+index ab2b752566d81..05cfa81d4c540 100644
+--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+@@ -265,6 +265,16 @@ static int a4xx_hw_init(struct msm_gpu *gpu)
+ if (ret)
+ return ret;
+
++ /*
++ * Use the default ringbuffer size and block size but disable the RPTR
++ * shadow
++ */
++ gpu_write(gpu, REG_A4XX_CP_RB_CNTL,
++ MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
++
++ /* Set the ringbuffer address */
++ gpu_write(gpu, REG_A4XX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));
++
+ /* Load PM4: */
+ ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data);
+ len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4;
+diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+index 4a484b06319ff..24b55103bfe00 100644
+--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+@@ -677,14 +677,21 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
+ if (ret)
+ return ret;
+
+- a5xx_preempt_hw_init(gpu);
+-
+ a5xx_gpmu_ucode_init(gpu);
+
+ ret = a5xx_ucode_init(gpu);
+ if (ret)
+ return ret;
+
++ /* Set the ringbuffer address */
++ gpu_write64(gpu, REG_A5XX_CP_RB_BASE, REG_A5XX_CP_RB_BASE_HI,
++ gpu->rb[0]->iova);
++
++ gpu_write(gpu, REG_A5XX_CP_RB_CNTL,
++ MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
++
++ a5xx_preempt_hw_init(gpu);
++
+ /* Disable the interrupts through the initial bringup stage */
+ gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
+
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+index ea073cd9d248e..dae32c6ac2120 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+@@ -550,6 +550,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+ if (ret)
+ goto out;
+
++ /* Set the ringbuffer address */
++ gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
++ gpu->rb[0]->iova);
++
++ gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
++ MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
++
+ /* Always come up on rb 0 */
+ a6xx_gpu->cur_ring = gpu->rb[0];
+
+diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+index 053da39da1cc0..3802ad38c519c 100644
+--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+@@ -354,26 +354,6 @@ int adreno_hw_init(struct msm_gpu *gpu)
+ ring->memptrs->rptr = 0;
+ }
+
+- /*
+- * Setup REG_CP_RB_CNTL. The same value is used across targets (with
+- * the excpetion of A430 that disables the RPTR shadow) - the cacluation
+- * for the ringbuffer size and block size is moved to msm_gpu.h for the
+- * pre-processor to deal with and the A430 variant is ORed in here
+- */
+- adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
+- MSM_GPU_RB_CNTL_DEFAULT |
+- (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
+-
+- /* Setup ringbuffer address - use ringbuffer[0] for GPU init */
+- adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_BASE,
+- REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
+-
+- if (!adreno_is_a430(adreno_gpu)) {
+- adreno_gpu_write64(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
+- REG_ADRENO_CP_RB_RPTR_ADDR_HI,
+- rbmemptr(gpu->rb[0], rptr));
+- }
+-
+ return 0;
+ }
+
+@@ -381,11 +361,8 @@ int adreno_hw_init(struct msm_gpu *gpu)
+ static uint32_t get_rptr(struct adreno_gpu *adreno_gpu,
+ struct msm_ringbuffer *ring)
+ {
+- if (adreno_is_a430(adreno_gpu))
+- return ring->memptrs->rptr = adreno_gpu_read(
+- adreno_gpu, REG_ADRENO_CP_RB_RPTR);
+- else
+- return ring->memptrs->rptr;
++ return ring->memptrs->rptr = adreno_gpu_read(
++ adreno_gpu, REG_ADRENO_CP_RB_RPTR);
+ }
+
+ struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
+--
+2.25.1
+
--- /dev/null
+From 161a7be6455794c1be2abce4bffc297ae31b7a0d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 3 Sep 2020 20:03:11 -0600
+Subject: drm/msm: Enable expanded apriv support for a650
+
+From: Jordan Crouse <jcrouse@codeaurora.org>
+
+[ Upstream commit 604234f33658cdd72f686be405a99646b397d0b3 ]
+
+a650 supports expanded apriv support that allows us to map critical buffers
+(ringbuffer and memstore) as as privileged to protect them from corruption.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++++-
+ drivers/gpu/drm/msm/msm_gpu.c | 2 +-
+ drivers/gpu/drm/msm/msm_gpu.h | 11 +++++++++++
+ drivers/gpu/drm/msm/msm_ringbuffer.c | 4 ++--
+ 4 files changed, 19 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+index c3a81594f4fb7..ea073cd9d248e 100644
+--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
++++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+@@ -533,7 +533,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
+ A6XX_PROTECT_RDONLY(0x980, 0x4));
+ gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
+
+- if (adreno_is_a650(adreno_gpu)) {
++ /* Enable expanded apriv for targets that support it */
++ if (gpu->hw_apriv) {
+ gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
+ (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
+ }
+@@ -908,6 +909,9 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
+ adreno_gpu->registers = NULL;
+ adreno_gpu->reg_offsets = a6xx_register_offsets;
+
++ if (adreno_is_a650(adreno_gpu))
++ adreno_gpu->base.hw_apriv = true;
++
+ ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
+ if (ret) {
+ a6xx_destroy(&(a6xx_gpu->base.base));
+diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
+index edd45f434ccd6..8653a2f7ae1c9 100644
+--- a/drivers/gpu/drm/msm/msm_gpu.c
++++ b/drivers/gpu/drm/msm/msm_gpu.c
+@@ -932,7 +932,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
+
+ memptrs = msm_gem_kernel_new(drm,
+ sizeof(struct msm_rbmemptrs) * nr_rings,
+- MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
++ check_apriv(gpu, MSM_BO_UNCACHED), gpu->aspace, &gpu->memptrs_bo,
+ &memptrs_iova);
+
+ if (IS_ERR(memptrs)) {
+diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
+index ab8f0f9c9dc88..15254239e5ec6 100644
+--- a/drivers/gpu/drm/msm/msm_gpu.h
++++ b/drivers/gpu/drm/msm/msm_gpu.h
+@@ -14,6 +14,7 @@
+ #include "msm_drv.h"
+ #include "msm_fence.h"
+ #include "msm_ringbuffer.h"
++#include "msm_gem.h"
+
+ struct msm_gem_submit;
+ struct msm_gpu_perfcntr;
+@@ -131,6 +132,8 @@ struct msm_gpu {
+ } devfreq;
+
+ struct msm_gpu_state *crashstate;
++ /* True if the hardware supports expanded apriv (a650 and newer) */
++ bool hw_apriv;
+ };
+
+ /* It turns out that all targets use the same ringbuffer size */
+@@ -319,4 +322,12 @@ static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
+ mutex_unlock(&gpu->dev->struct_mutex);
+ }
+
++/*
++ * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
++ * support expanded privileges
++ */
++#define check_apriv(gpu, flags) \
++ (((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))
++
++
+ #endif /* __MSM_GPU_H__ */
+diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
+index 39ecb5a18431e..935bf9b1d9418 100644
+--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
++++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
+@@ -27,8 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
+ ring->id = id;
+
+ ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
+- MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
+- &ring->iova);
++ check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY),
++ gpu->aspace, &ring->bo, &ring->iova);
+
+ if (IS_ERR(ring->start)) {
+ ret = PTR_ERR(ring->start);
+--
+2.25.1
+
--- /dev/null
+From e27201faed9dcd564060e752bf925e7917dc9b80 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 17 Aug 2020 09:23:09 -0700
+Subject: drm/msm/gpu: make ringbuffer readonly
+
+From: Rob Clark <robdclark@chromium.org>
+
+[ Upstream commit 352c83fb39cae3eff95a8e1ed23006291abb6196 ]
+
+The GPU has no business writing into the ringbuffer, let's make it
+readonly to the GPU.
+
+Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support")
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
+index e397c44cc0112..39ecb5a18431e 100644
+--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
++++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
+@@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
+ ring->id = id;
+
+ ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
+- MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova);
++ MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
++ &ring->iova);
+
+ if (IS_ERR(ring->start)) {
+ ret = PTR_ERR(ring->start);
+--
+2.25.1
+
usb-serial-option-add-support-for-sim7070-sim7080-sim7090-modules.patch
usb-fix-out-of-sync-data-toggle-if-a-configured-device-is-reconfigured.patch
usb-typec-ucsi-acpi-check-the-_dep-dependencies.patch
+drm-msm-gpu-make-ringbuffer-readonly.patch
+drm-msm-a6xx-update-a6xx_hw_init-for-a640-and-a650.patch
+drm-msm-enable-expanded-apriv-support-for-a650.patch
+drm-msm-disable-the-rptr-shadow.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
