]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
tcg: Always define TARGET_INSN_START_EXTRA_WORDS
authorPhilippe Mathieu-Daudé <philmd@linaro.org>
Wed, 19 Mar 2025 11:46:55 +0000 (12:46 +0100)
committerRichard Henderson <richard.henderson@linaro.org>
Wed, 23 Apr 2025 22:07:32 +0000 (15:07 -0700)
Do not define TARGET_INSN_START_EXTRA_WORDS under the
hood, have each target explicitly define it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
include/tcg/insn-start-words.h
include/tcg/tcg-op.h
target/alpha/cpu-param.h
target/avr/cpu-param.h
target/hexagon/cpu-param.h
target/loongarch/cpu-param.h
target/ppc/cpu-param.h
target/rx/cpu-param.h
target/tricore/cpu-param.h
target/xtensa/cpu-param.h

index c439c09f2feb61ea7bf5a7d02e904b7f8f2797cc..d416d19bcf95f1b961b3c857a8e3fff38b4434ee 100644 (file)
@@ -8,10 +8,6 @@
 
 #include "cpu-param.h"
 
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
 
 #endif /* TARGET_INSN_START_WORDS */
index bc46b5570c41fcee74f2ea9cd4d1ee1294b735b1..cded92a4479bb86192ccf2de6755c426f948ce8e 100644 (file)
@@ -23,7 +23,7 @@
 # error
 #endif
 
-#ifndef TARGET_INSN_START_EXTRA_WORDS
+#if TARGET_INSN_START_EXTRA_WORDS == 0
 static inline void tcg_gen_insn_start(target_ulong pc)
 {
     TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
index 63989e71c0609e4f9c382109f90731cd30f528d2..dd44feb17933d8525e3333577832ad0d86eb067c 100644 (file)
@@ -24,6 +24,8 @@
 # define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 /* Alpha processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)
 
index f5248ce9e794c4777743480658ae4dbd11e5d467..9d37848d97d7a03c63241c6b3ed671df029818d6 100644 (file)
@@ -25,6 +25,8 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 24
 #define TARGET_VIRT_ADDR_SPACE_BITS 24
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #endif
index 45ee7b46409c7a68b1fbb0d92f09fc2636be005a..635d509e743633bc01ba625fd44a683ef3e750db 100644 (file)
@@ -23,4 +23,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 36
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
index 52437946e56ca566cb69415a2e8b975b2cdfd215..dbe414bb35a91850c76c4db0298f4e7ae801a60c 100644 (file)
@@ -13,6 +13,8 @@
 
 #define TARGET_PAGE_BITS 12
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO (0)
 
 #endif
index 553ad2f4c6a27e697df6da5c26ac7dbd0e6fc2b8..d0651d2ac89898f46a665d6556278a3c2361cd96 100644 (file)
@@ -37,6 +37,8 @@
 # define TARGET_PAGE_BITS 12
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #define TCG_GUEST_DEFAULT_MO 0
 
 #endif
index ef1970a09e93e4d702ed0ccd2da51f7a8f1dad4c..84934f3bcaf0e775dc1ca9503e85255806e5b1b8 100644 (file)
@@ -24,4 +24,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
index 790242ef3d222295816638f5343e84756dd14e71..eb33a67c41943293969b651a40eb5c850d356f6f 100644 (file)
@@ -12,4 +12,6 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 #endif
index 5e4848ad059c6eea2dfc1a4e5d05c96f2b1c8325..e7cb747aaae1331d96121852cc779912b28244a5 100644 (file)
@@ -16,6 +16,8 @@
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
 /* Xtensa processors have a weak memory model */
 #define TCG_GUEST_DEFAULT_MO      (0)