#include "cpu-param.h"
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
#endif /* TARGET_INSN_START_WORDS */
# error
#endif
-#ifndef TARGET_INSN_START_EXTRA_WORDS
+#if TARGET_INSN_START_EXTRA_WORDS == 0
static inline void tcg_gen_insn_start(target_ulong pc)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO 0
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
#define TARGET_PAGE_BITS 12
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO (0)
#endif
# define TARGET_PAGE_BITS 12
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#define TCG_GUEST_DEFAULT_MO 0
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
#endif
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 0
+
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)