mtd: spi-nor: core: Check read CR support

Some SPI controllers like Intel's one on the PCI bus do not support
opcode 35h. This opcode is used to read the Configuration Register on
SPI-NOR chips that have 16-bit Status Register configured regardless
of the controller support for it. Adding a check call in the setup step
allows disabling use of the 35h opcode and falling back to the manual
Status Registers management.

Before:
openat(AT_FDCWD, "/dev/mtd0", O_RDWR)   = 4
ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = -1
EOPNOTSUPP

After:
openat(AT_FDCWD, "/dev/mtd0", O_RDWR)   = 4
ioctl(4, MIXER_WRITE(6) or MEMUNLOCK, {start=0, length=0x2000000}) = 0
ioctl(4, MIXER_WRITE(5) or MEMLOCK, {start=0x1800000, length=0x800000}) = 0

Suggested-by: Adeel Arshad <adeel.arshad@intel.com>
Signed-off-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 20ea80450f222242761878ebdb3dcdcca1e8877a..d3f8a78efd3bf9032b807e81b7a8b77556367e71 100644 (file)
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -2459,6 +2459,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)
                                            &params->page_programs[ppidx]))
                        *hwcaps &= ~BIT(cap);
        }
+
+       /* Some SPI controllers might not support CR read opcode. */
+       if (!(nor->flags & SNOR_F_NO_READ_CR)) {
+               struct spi_mem_op op = SPI_NOR_RDCR_OP(nor->bouncebuf);
+
+               spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
+
+               if (spi_nor_spimem_check_op(nor, &op))
+                       nor->flags |= SNOR_F_NO_READ_CR;
+       }
 }
 
 /**