.irqp_used = 1,
.soc_mclk = true,
.irq_reg_offset = 0x1a00,
- .i2s_pin_cfg_offset = 0x1440,
- .i2s_mode = 0x0a,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x03802800,
};
.no_of_ctrls = 1,
.irqp_used = 0,
.irq_reg_offset = 0x1800,
- .i2s_pin_cfg_offset = 0x1400,
- .i2s_mode = 0x04,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x02052800,
};
.irqp_used = 1,
.soc_mclk = true,
.irq_reg_offset = 0x1a00,
- .i2s_pin_cfg_offset = 0x1440,
- .i2s_mode = 0x0a,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x03802800,
};
.irqp_used = 1,
.soc_mclk = true,
.irq_reg_offset = 0x1a00,
- .i2s_pin_cfg_offset = 0x1440,
- .i2s_mode = 0x0a,
.scratch_reg_offset = 0x12800,
.sram_pte_offset = 0x03802800,
};
int irqp_used;
bool soc_mclk;
u32 irq_reg_offset;
- u32 i2s_pin_cfg_offset;
- int i2s_mode;
u64 scratch_reg_offset;
u64 sram_pte_offset;
};