arm64/boot: Factor out a macro to check SPE version

We check the version of SPE twice, and we'll add one more check in the
next commit so factor out a macro to do this. Change the #3 magic number
to the actual SPE version define (V1p2) to make it more readable.

No functional changes intended.

Tested-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 46033027510ccadc79359bb47e211137cae2c102..a305386eb2e379d08389397d412ad9be3dadcae4 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -91,6 +91,14 @@
        msr     cntvoff_el2, xzr                // Clear virtual offset
 .endm
 
+/* Branch to skip_label if SPE version is less than given version */
+.macro __spe_vers_imp skip_label, version, tmp
+    mrs    \tmp, id_aa64dfr0_el1
+    ubfx   \tmp, \tmp, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
+    cmp    \tmp, \version
+    b.lt   \skip_label
+.endm
+
 .macro __init_el2_debug
        mrs     x1, id_aa64dfr0_el1
        ubfx    x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
@@ -103,8 +111,7 @@
        csel    x2, xzr, x0, eq                 // all PMU counters from EL1
 
        /* Statistical profiling */
-       ubfx    x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
-       cbz     x0, .Lskip_spe_\@               // Skip if SPE not present
+       __spe_vers_imp .Lskip_spe_\@, ID_AA64DFR0_EL1_PMSVer_IMP, x0 // Skip if SPE not present
 
        mrs_s   x0, SYS_PMBIDR_EL1              // If SPE available at EL2,
        and     x0, x0, #(1 << PMBIDR_EL1_P_SHIFT)
@@ -263,10 +270,8 @@
 
        mov     x0, xzr
        mov     x2, xzr
-       mrs     x1, id_aa64dfr0_el1
-       ubfx    x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
-       cmp     x1, #3
-       b.lt    .Lskip_spe_fgt_\@
+       /* If SPEv1p2 is implemented, */
+       __spe_vers_imp .Lskip_spe_fgt_\@, #ID_AA64DFR0_EL1_PMSVer_V1P2, x1
        /* Disable PMSNEVFR_EL1 read and write traps */
        orr     x0, x0, #HDFGRTR_EL2_nPMSNEVFR_EL1_MASK
        orr     x2, x2, #HDFGWTR_EL2_nPMSNEVFR_EL1_MASK