It did not connect SPI IRQ to the Interrupt Controller, so even the SPI
model raised the IRQ, the interrupt was not received. The CPU therefore
did not trigger an interrupt via the controller, and the firmware never
received the interrupt.
Fixes: 356b230ed13889e09d087a96498887de695df17e ("aspeed/soc: Add AST1030 support")
Fixes: f25c0ae1079dc0b9de02676eb3e3949a09df9f41 ("aspeed/soc: Add AST2600 support")
Fixes: 5dd883ab0635c9f715c77cc32622e458a0724581 ("aspeed/soc: Add AST2700 support")
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251106084925.1253704-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* Secure Boot Controller */
sc->memmap[ASPEED_DEV_SPI1 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 + i));
}
/* EHCI */
sc->memmap[ASPEED_DEV_SPI0 + i]);
aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1,
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 + i));
}
/* EHCI */