+++ /dev/null
-From d3ec3a08fa700c8b46abb137dce4e2514a6f9668 Mon Sep 17 00:00:00 2001
-From: Marc Zyngier <maz@kernel.org>
-Date: Thu, 7 Feb 2019 16:01:21 +0000
-Subject: arm64: KVM: Trap VM ops when ARM64_WORKAROUND_CAVIUM_TX2_219_TVM is set
-
-From: Marc Zyngier <marc.zyngier@arm.com>
-
-commit d3ec3a08fa700c8b46abb137dce4e2514a6f9668 upstream.
-
-In order to workaround the TX2-219 erratum, it is necessary to trap
-TTBRx_EL1 accesses to EL2. This is done by setting HCR_EL2.TVM on
-guest entry, which has the side effect of trapping all the other
-VM-related sysregs as well.
-
-To minimize the overhead, a fast path is used so that we don't
-have to go all the way back to the main sysreg handling code,
-unless the rest of the hypervisor expects to see these accesses.
-
-Cc: <stable@vger.kernel.org>
-Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-Signed-off-by: Will Deacon <will@kernel.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
----
- arch/arm64/include/asm/cpucaps.h | 3 +
- arch/arm64/kvm/hyp/switch.c | 69 +++++++++++++++++++++++++++++++++++++--
- 2 files changed, 69 insertions(+), 3 deletions(-)
-
---- a/arch/arm64/include/asm/cpucaps.h
-+++ b/arch/arm64/include/asm/cpucaps.h
-@@ -53,7 +53,8 @@
- #define ARM64_HAS_STAGE2_FWB 32
- #define ARM64_WORKAROUND_1463225 33
- #define ARM64_SSBS 34
-+#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 35
-
--#define ARM64_NCAPS 35
-+#define ARM64_NCAPS 36
-
- #endif /* __ASM_CPUCAPS_H */
---- a/arch/arm64/kvm/hyp/switch.c
-+++ b/arch/arm64/kvm/hyp/switch.c
-@@ -130,6 +130,9 @@ static void __hyp_text __activate_traps(
- {
- u64 hcr = vcpu->arch.hcr_el2;
-
-+ if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
-+ hcr |= HCR_TVM;
-+
- write_sysreg(hcr, hcr_el2);
-
- if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE))
-@@ -172,8 +175,10 @@ static void __hyp_text __deactivate_trap
- * the crucial bit is "On taking a vSError interrupt,
- * HCR_EL2.VSE is cleared to 0."
- */
-- if (vcpu->arch.hcr_el2 & HCR_VSE)
-- vcpu->arch.hcr_el2 = read_sysreg(hcr_el2);
-+ if (vcpu->arch.hcr_el2 & HCR_VSE) {
-+ vcpu->arch.hcr_el2 &= ~HCR_VSE;
-+ vcpu->arch.hcr_el2 |= read_sysreg(hcr_el2) & HCR_VSE;
-+ }
-
- if (has_vhe())
- deactivate_traps_vhe();
-@@ -379,6 +384,61 @@ static bool __hyp_text __hyp_switch_fpsi
- return true;
- }
-
-+static bool __hyp_text handle_tx2_tvm(struct kvm_vcpu *vcpu)
-+{
-+ u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_hsr(vcpu));
-+ int rt = kvm_vcpu_sys_get_rt(vcpu);
-+ u64 val = vcpu_get_reg(vcpu, rt);
-+
-+ /*
-+ * The normal sysreg handling code expects to see the traps,
-+ * let's not do anything here.
-+ */
-+ if (vcpu->arch.hcr_el2 & HCR_TVM)
-+ return false;
-+
-+ switch (sysreg) {
-+ case SYS_SCTLR_EL1:
-+ write_sysreg_el1(val, SYS_SCTLR);
-+ break;
-+ case SYS_TTBR0_EL1:
-+ write_sysreg_el1(val, SYS_TTBR0);
-+ break;
-+ case SYS_TTBR1_EL1:
-+ write_sysreg_el1(val, SYS_TTBR1);
-+ break;
-+ case SYS_TCR_EL1:
-+ write_sysreg_el1(val, SYS_TCR);
-+ break;
-+ case SYS_ESR_EL1:
-+ write_sysreg_el1(val, SYS_ESR);
-+ break;
-+ case SYS_FAR_EL1:
-+ write_sysreg_el1(val, SYS_FAR);
-+ break;
-+ case SYS_AFSR0_EL1:
-+ write_sysreg_el1(val, SYS_AFSR0);
-+ break;
-+ case SYS_AFSR1_EL1:
-+ write_sysreg_el1(val, SYS_AFSR1);
-+ break;
-+ case SYS_MAIR_EL1:
-+ write_sysreg_el1(val, SYS_MAIR);
-+ break;
-+ case SYS_AMAIR_EL1:
-+ write_sysreg_el1(val, SYS_AMAIR);
-+ break;
-+ case SYS_CONTEXTIDR_EL1:
-+ write_sysreg_el1(val, SYS_CONTEXTIDR);
-+ break;
-+ default:
-+ return false;
-+ }
-+
-+ __kvm_skip_instr(vcpu);
-+ return true;
-+}
-+
- /*
- * Return true when we were able to fixup the guest exit and should return to
- * the guest, false when we should restore the host state and return to the
-@@ -398,6 +458,11 @@ static bool __hyp_text fixup_guest_exit(
- if (*exit_code != ARM_EXCEPTION_TRAP)
- goto exit;
-
-+ if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
-+ kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_SYS64 &&
-+ handle_tx2_tvm(vcpu))
-+ return true;
-+
- /*
- * We trap the first access to the FP/SIMD to save the host context
- * and restore the guest context lazily.
cpufreq-imx6q-read-ocotp-through-nvmem-for-imx6ul-imx6ull.patch
arm-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
pci-switchtec-read-all-64-bits-of-part_event_bitmap.patch
-arm64-kvm-trap-vm-ops-when-arm64_workaround_cavium_tx2_219_tvm-is-set.patch
gtp-fix-bad-unlock-balance-in-gtp_encap_enable_socket.patch
macvlan-do-not-assume-mac_header-is-set-in-macvlan_broadcast.patch
net-dsa-mv88e6xxx-preserve-priority-when-setting-cpu-port.patch
+++ /dev/null
-From b908baf1e72f2a84843354ddf714afb9436315e4 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 20 Jun 2019 16:12:36 -0600
-Subject: coresight: etb10: Do not call smp_processor_id from preemptible
-
-From: Suzuki K Poulose <suzuki.poulose@arm.com>
-
-[ Upstream commit 730766bae3280a25d40ea76a53dc6342e84e6513 ]
-
-During a perf session we try to allocate buffers on the "node" associated
-with the CPU the event is bound to. If it is not bound to a CPU, we
-use the current CPU node, using smp_processor_id(). However this is unsafe
-in a pre-emptible context and could generate the splats as below :
-
- BUG: using smp_processor_id() in preemptible [00000000] code: perf/2544
-
-Use NUMA_NO_NODE hint instead of using the current node for events
-not bound to CPUs.
-
-Fixes: 2997aa4063d97fdb39 ("coresight: etb10: implementing AUX API")
-Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
-Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
-Cc: stable <stable@vger.kernel.org> # 4.6+
-Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
-Link: https://lore.kernel.org/r/20190620221237.3536-5-mathieu.poirier@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/hwtracing/coresight/coresight-etb10.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
-index ace55385b26f..245c32b52355 100644
---- a/drivers/hwtracing/coresight/coresight-etb10.c
-+++ b/drivers/hwtracing/coresight/coresight-etb10.c
-@@ -279,9 +279,7 @@ static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu,
- int node;
- struct cs_buffers *buf;
-
-- if (cpu == -1)
-- cpu = smp_processor_id();
-- node = cpu_to_node(cpu);
-+ node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu);
-
- buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
- if (!buf)
---
-2.20.1
-
+++ /dev/null
-From 1737e8b3428030726119aa43a00563693aa16264 Mon Sep 17 00:00:00 2001
-From: Sasha Levin <sashal@kernel.org>
-Date: Thu, 20 Jun 2019 16:12:35 -0600
-Subject: coresight: tmc-etf: Do not call smp_processor_id from preemptible
-
-From: Suzuki K Poulose <suzuki.poulose@arm.com>
-
-[ Upstream commit 024c1fd9dbcc1d8a847f1311f999d35783921b7f ]
-
-During a perf session we try to allocate buffers on the "node" associated
-with the CPU the event is bound to. If it is not bound to a CPU, we
-use the current CPU node, using smp_processor_id(). However this is unsafe
-in a pre-emptible context and could generate the splats as below :
-
- BUG: using smp_processor_id() in preemptible [00000000] code: perf/2544
- caller is tmc_alloc_etf_buffer+0x5c/0x60
- CPU: 2 PID: 2544 Comm: perf Not tainted 5.1.0-rc6-147786-g116841e #344
- Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Feb 1 2019
- Call trace:
- dump_backtrace+0x0/0x150
- show_stack+0x14/0x20
- dump_stack+0x9c/0xc4
- debug_smp_processor_id+0x10c/0x110
- tmc_alloc_etf_buffer+0x5c/0x60
- etm_setup_aux+0x1c4/0x230
- rb_alloc_aux+0x1b8/0x2b8
- perf_mmap+0x35c/0x478
- mmap_region+0x34c/0x4f0
- do_mmap+0x2d8/0x418
- vm_mmap_pgoff+0xd0/0xf8
- ksys_mmap_pgoff+0x88/0xf8
- __arm64_sys_mmap+0x28/0x38
- el0_svc_handler+0xd8/0x138
- el0_svc+0x8/0xc
-
-Use NUMA_NO_NODE hint instead of using the current node for events
-not bound to CPUs.
-
-Fixes: 2e499bbc1a929ac ("coresight: tmc: implementing TMC-ETF AUX space API")
-Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
-Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
-Cc: stable <stable@vger.kernel.org> # 4.7+
-Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
-Link: https://lore.kernel.org/r/20190620221237.3536-4-mathieu.poirier@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- drivers/hwtracing/coresight/coresight-tmc-etf.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
-
-diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
-index 14df4e34c21c..faf68412eb92 100644
---- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
-+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
-@@ -292,9 +292,7 @@ static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu,
- int node;
- struct cs_buffers *buf;
-
-- if (cpu == -1)
-- cpu = smp_processor_id();
-- node = cpu_to_node(cpu);
-+ node = (event->cpu == -1) ? NUMA_NO_NODE : cpu_to_node(event->cpu);
-
- /* Allocate memory structure for interaction with Perf */
- buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node);
---
-2.20.1
-
fix-compat-handling-of-ficlonerange-fideduperange-and-fs_ioc_fiemap.patch
drm-mst-fix-mst-sideband-up-reply-failure-handling.patch
powerpc-pseries-hvconsole-fix-stack-overread-via-udb.patch
-coresight-tmc-etf-do-not-call-smp_processor_id-from-.patch
-coresight-etb10-do-not-call-smp_processor_id-from-pr.patch
rxrpc-fix-possible-null-pointer-access-in-icmp-handl.patch
ath9k_htc-modify-byte-order-for-an-error-message.patch
ath9k_htc-discard-undersized-packets.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
