rs6000: Rework vector float comparison in rs6000_emit_vector_compare - p2

All kinds of vector float comparison operators have been
supported in a rtl comparison pattern as vector.md, we can
just emit an rtx comparison insn with the given comparison
operator in function rs6000_emit_vector_compare instead of
checking and handling the reverse condition cases.

This is part 2, it further checks for comparison opeators
NE/UNLE/UNLT.  In rs6000_emit_vector_compare, they are
handled with reversed code which is queried from function
reverse_condition_maybe_unordered and inverting with
one_cmpl_optab.  It's the same as what we have in vector.md:

; ne(a,b)   = ~eq(a,b)
; unle(a,b) = ~gt(a,b)
; unlt(a,b) = ~ge(a,b)

The operators on the right side have been supported in part 1.
This patch should not have any functionality change too.

gcc/ChangeLog:

	* config/rs6000/rs6000.cc (rs6000_emit_vector_compare): Emit rtx
	comparison for operators NE/UNLE/UNLT of MODE_VECTOR_FLOAT directly.

diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 692acbb7653555294cbf62d93ca6bacf06873e75..793fb95b660b3588c80855e823a0cf5840262c69 100644 (file)
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -16049,20 +16049,18 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
      comparison operators in a comparison rtl pattern, we can
      just emit the comparison rtx insn directly here.  Besides,
      we should have a centralized place to handle the possibility
-     of raising invalid exception.  As the first step, only check
-     operators EQ/GT/GE/UNORDERED/ORDERED/LTGT/UNEQ for now, they
-     are handled equivalently as before.
+     of raising invalid exception.  For EQ/GT/GE/UNORDERED/
+     ORDERED/LTGT/UNEQ, they are handled equivalently as before;
+     for NE/UNLE/UNLT, they are handled with reversed code
+     and inverting, it's the same as before.
 
      FIXME: Handle the remaining vector float comparison operators
      here.  */
   if (GET_MODE_CLASS (dmode) == MODE_VECTOR_FLOAT
-      && (rcode == EQ
-         || rcode == GT
-         || rcode == GE
-         || rcode == UNORDERED
-         || rcode == ORDERED
-         || rcode == LTGT
-         || rcode == UNEQ))
+      && rcode != LT
+      && rcode != LE
+      && rcode != UNGE
+      && rcode != UNGT)
     {
       mask = gen_reg_rtx (dmode);
       emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (rcode, dmode, op0, op1)));
@@ -16090,8 +16088,6 @@ rs6000_emit_vector_compare (enum rtx_code rcode,
       try_again = true;
       break;
     case NE:
-    case UNLE:
-    case UNLT:
     case UNGE:
     case UNGT:
       /* Invert condition and try again.