arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off

Fix SD card removal caused by automatic LDO5 power off after boot:

LDO5: disabling
mmc1: card 59b4 removed
EXT4-fs (mmcblk1p2): shut down requested (2)
Aborting journal on device mmcblk1p2-8.
JBD2: I/O error when updating journal superblock for mmcblk1p2-8.

To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled
regulator that is supplied by LDO5. Since this is implemented on SoM but
used on baseboards with SD-card interface, implement the functionality
on SoM part and optionally enable it on baseboards if needed.

Fixes: 418d1d840e42 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
index d7fd9d36f8240eb2b972548164458678d90d0255..f7346b3d35fe5396eac355fc8b5bc1c0318efb98 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
@@ -467,6 +467,10 @@
        status = "okay";
 };
 
+&reg_usdhc2_vqmmc {
+       status = "okay";
+};
+
 &sai5 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai5>;
@@ -876,8 +880,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d2>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d2>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d2>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -886,8 +889,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -896,8 +898,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>;
        };
 
        pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
index 33cd92e63c5d5ff7b2e21deda30e66b78e9468dc..4eedd00d83b9fcf64bb43f5b29643bd43dfe0a60 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
@@ -604,6 +604,10 @@
        status = "okay";
 };
 
+&reg_usdhc2_vqmmc {
+       status = "okay";
+};
+
 &sai3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai3>;
@@ -983,8 +987,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d2>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d2>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d2>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
@@ -993,8 +996,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
@@ -1003,8 +1005,7 @@
                           <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
                           <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
-                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
-                          <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
+                          <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>;
        };
 
        pinctrl_usdhc2_gpio: usdhc2-gpiogrp {

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
index fd70b686e7efc023506d83b7836e441bb08efbbc..b48d5da1472739ef81716d3a9f7869793c78370e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi
@@ -24,6 +24,20 @@
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
        };
+
+       reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+               compatible = "regulator-gpio";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
+               regulator-name = "V_SD2";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <3300000>;
+               gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+               states = <1800000 0x1>,
+                        <3300000 0x0>;
+               vin-supply = <&ldo5_reg>;
+               status = "disabled";
+       };
 };
 
 &A53_0 {
@@ -184,6 +198,10 @@
        };
 };
 
+&usdhc2 {
+       vqmmc-supply = <&reg_usdhc2_vqmmc>;
+};
+
 &usdhc3 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc3>;
@@ -233,6 +251,10 @@
                fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19        0x10>;
        };
 
+       pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp {
+               fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04         0xc0>;
+       };
+
        pinctrl_usdhc3: usdhc3grp {
                fsl,pins = <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK          0x194>,
                           <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD          0x1d4>,