RISC-V: Fix ICE for expand_select_vldi [PR120652]

The will be one ICE when expand pass, the bt similar as below.

during RTL pass: expand
red.c: In function 'main':
red.c:20:5: internal compiler error: in require, at machmode.h:323
   20 | int main() {
      |     ^~~~
0x2e0b1d6 internal_error(char const*, ...)
        ../../../gcc/gcc/diagnostic-global-context.cc:517
0xd0d3ed fancy_abort(char const*, int, char const*)
        ../../../gcc/gcc/diagnostic.cc:1803
0xc3da74 opt_mode<machine_mode>::require() const
        ../../../gcc/gcc/machmode.h:323
0xc3de2f opt_mode<machine_mode>::require() const
        ../../../gcc/gcc/poly-int.h:1383
0xc3de2f riscv_vector::expand_select_vl(rtx_def**)
        ../../../gcc/gcc/config/riscv/riscv-v.cc:4218
0x21c7d22 gen_select_vldi(rtx_def*, rtx_def*, rtx_def*)
        ../../../gcc/gcc/config/riscv/autovec.md:1344
0x134db6c maybe_expand_insn(insn_code, unsigned int, expand_operand*)
        ../../../gcc/gcc/optabs.cc:8257
0x134db6c expand_insn(insn_code, unsigned int, expand_operand*)
        ../../../gcc/gcc/optabs.cc:8288
0x11b21d3 expand_fn_using_insn
        ../../../gcc/gcc/internal-fn.cc:318
0xef32cf expand_call_stmt
        ../../../gcc/gcc/cfgexpand.cc:3097
0xef32cf expand_gimple_stmt_1
        ../../../gcc/gcc/cfgexpand.cc:4264
0xef32cf expand_gimple_stmt
        ../../../gcc/gcc/cfgexpand.cc:4411
0xef95b6 expand_gimple_basic_block
        ../../../gcc/gcc/cfgexpand.cc:6472
0xefb66f execute
        ../../../gcc/gcc/cfgexpand.cc:7223

The select_vl op_1 and op_2 may be the same const_int like (const_int 32).
And then maybe_legitimize_operands will:

1. First mov the const op_1 to a reg.
2. Resue the reg of op_1 for op_2 as the op_1 and op_2 is equal.

That will break the assumption that the op_2 of select_vl is immediate,
or something like CONST_INT_POLY.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

	PR target/120652

gcc/ChangeLog:

	* config/riscv/autovec.md: Add immediate_operand for
	select_vl operand 2.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr120652-1.c: New test.
	* gcc.target/riscv/rvv/autovec/pr120652-2.c: New test.
	* gcc.target/riscv/rvv/autovec/pr120652-3.c: New test.
	* gcc.target/riscv/rvv/autovec/pr120652.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index c678eefc700314bd9984b6b6054b7e471a357353..94a61bdc5cf5f6a13a2ebd73c01c4a5bcb5eb625 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1338,7 +1338,7 @@
 (define_expand "select_vl<mode>"
   [(match_operand:P 0 "register_operand")
    (match_operand:P 1 "vector_length_operand")
-   (match_operand:P 2 "")]
+   (match_operand:P 2 "immediate_operand")]
   "TARGET_VECTOR"
 {
   riscv_vector::expand_select_vl (operands);

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c
new file mode 100644 (file)
index 0000000..260e4c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl256b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c
new file mode 100644 (file)
index 0000000..6f85942
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl512b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c
new file mode 100644 (file)
index 0000000..9852b5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c
@@ -0,0 +1,5 @@
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zvl1024b -mabi=lp64d -O3" } */
+
+#include "pr120652.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h
new file mode 100644 (file)
index 0000000..75f2716
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h
@@ -0,0 +1,31 @@
+#ifndef HAVE_DEFINED_PR120652_H
+#define HAVE_DEFINED_PR120652_H
+
+unsigned n;
+char ab[6];
+unsigned ac;
+unsigned ae;
+
+int ak(int bb) {
+bd:
+  for (ac = -17; ac != 16; ac++) {
+    unsigned be = 95;
+    if (be <= n) {
+      char *bg = &ab[1];
+      *bg ^= bb;
+    } else {
+      ae--;
+      for (n = 8; 0;)
+       goto bd;
+    }
+  }
+  return 0;
+}
+
+int main() {
+  ak(7);
+
+  return 0;
+}
+
+#endif