arm: dts: agilex5: Update CCU configuration

Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.

Signed-off-by: Tingting Meng <tingting.meng@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index b34af85c58d4d5aa5896d7a5bfcc663efa227b98..874e71b5ca4b995fff52a0c8b0d16d0324224a33 100644 (file)
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -208,7 +208,8 @@
                                intel,offset-settings =
                                        /* DMIUSMCTCR */
                                        <0x00000300 0x00000001 0x00000003>,
-                                       <0x00000300 0x00000003 0x00000003>;
+                                       <0x00000300 0x00000003 0x00000003>,
+                                       <0x00000308 0x00000004 0x0000001F>;
                                bootph-all;
                        };
 
@@ -218,7 +219,8 @@
                                intel,offset-settings =
                                        /* DMIUSMCTCR */
                                        <0x00000300 0x00000001 0x00000003>,
-                                       <0x00000300 0x00000003 0x00000003>;
+                                       <0x00000300 0x00000003 0x00000003>,
+                                       <0x00000308 0x00000004 0x0000001F>;
                                bootph-all;
                        };
                };