net: stmmac: meson8b: use phy_intf_sel directly

Rearrange meson_axg_set_phy_mode() to use phy_intf_sel directly,
converting it to the register field for meson8b_dwmac_mask_bits().

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vIT6W-0000000DpPR-0tby@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index f485b9b858bf69bda6dec790e3d58ac967b43ef9..865cd61661342e2166a4c90fb97862316c98df3b 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -26,8 +26,6 @@
 #define PRG_ETH0_RGMII_MODE            BIT(0)
 
 #define PRG_ETH0_EXT_PHY_MODE_MASK     GENMASK(2, 0)
-#define PRG_ETH0_EXT_RGMII_MODE                PHY_INTF_SEL_RGMII
-#define PRG_ETH0_EXT_RMII_MODE         PHY_INTF_SEL_RMII
 
 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
 #define PRG_ETH0_CLK_M250_SEL_MASK     GENMASK(4, 4)
@@ -238,21 +236,19 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
 
 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
 {
+       int phy_intf_sel;
+
        switch (dwmac->phy_mode) {
        case PHY_INTERFACE_MODE_RGMII:
        case PHY_INTERFACE_MODE_RGMII_RXID:
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_RGMII_TXID:
                /* enable RGMII mode */
-               meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
-                                       PRG_ETH0_EXT_PHY_MODE_MASK,
-                                       PRG_ETH0_EXT_RGMII_MODE);
+               phy_intf_sel = PHY_INTF_SEL_RGMII;
                break;
        case PHY_INTERFACE_MODE_RMII:
                /* disable RGMII mode -> enables RMII mode */
-               meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
-                                       PRG_ETH0_EXT_PHY_MODE_MASK,
-                                       PRG_ETH0_EXT_RMII_MODE);
+               phy_intf_sel = PHY_INTF_SEL_RMII;
                break;
        default:
                dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -260,6 +256,10 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
                return -EINVAL;
        }
 
+       meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_EXT_PHY_MODE_MASK,
+                               FIELD_PREP(PRG_ETH0_EXT_PHY_MODE_MASK,
+                                          phy_intf_sel));
+
        return 0;
 }