]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
hw/intc/loongarch_pch: Discard write operation with ISR register
authorBibo Mao <maobibo@loongson.cn>
Wed, 7 May 2025 02:31:38 +0000 (10:31 +0800)
committerSong Gao <gaosong@loongson.cn>
Wed, 14 May 2025 07:46:08 +0000 (15:46 +0800)
With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-7-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
hw/intc/loongarch_pch_pic.c

index 9b64bf938fda968d9049e7432593f772f2cbd5d1..e6fcf645eb565f51578f94d2f3fe05a4f0db2c6f 100644 (file)
@@ -234,12 +234,6 @@ static void loongarch_pch_pic_high_writew(void *opaque, hwaddr addr,
     trace_loongarch_pch_pic_high_writew(size, addr, data);
 
     switch (addr) {
-    case PCH_PIC_INT_STATUS:
-        s->intisr = get_writew_val(s->intisr, data, 0);
-        break;
-    case PCH_PIC_INT_STATUS + 4:
-        s->intisr = get_writew_val(s->intisr, data, 1);
-        break;
     case PCH_PIC_INT_POL:
         s->int_polarity = get_writew_val(s->int_polarity, data, 0);
         break;