clk: samsung: update PLL locktime for PLL142XX used on FSD platform

Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence
update PLL142XX controller locktime to 150.

Cc: stable@vger.kernel.org
Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support")
Signed-off-by: Varada Pavani <v.pavani@samsung.com>
Link: https://lore.kernel.org/r/20250225131918.50925-3-v.pavani@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 2e94bba6c3966b9470f0ef42ad101ee3da0519b9..023a25af73c473eb6c82a34689b8cefe2316dec9 100644 (file)
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -206,6 +206,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
  */
 /* Maximum lock time can be 270 * PDIV cycles */
 #define PLL35XX_LOCK_FACTOR    (270)
+#define PLL142XX_LOCK_FACTOR   (150)
 
 #define PLL35XX_MDIV_MASK       (0x3FF)
 #define PLL35XX_PDIV_MASK       (0x3F)
@@ -272,7 +273,11 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
        }
 
        /* Set PLL lock time. */
-       writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
+       if (pll->type == pll_142xx)
+               writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR,
+                       pll->lock_reg);
+       else
+               writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
                        pll->lock_reg);
 
        /* Change PLL PMS values */