--- /dev/null
+From 69c3ed7282a143439bbc2d03dc00d49c68fcb629 Mon Sep 17 00:00:00 2001
+From: Pan Bian <bianpan2016@163.com>
+Date: Wed, 20 Jan 2021 01:16:08 -0800
+Subject: drm/imx: fix memory leak when fails to init
+
+From: Pan Bian <bianpan2016@163.com>
+
+commit 69c3ed7282a143439bbc2d03dc00d49c68fcb629 upstream.
+
+Put DRM device on initialization failure path rather than directly
+return error code.
+
+Fixes: a67d5088ceb8 ("drm/imx: drop explicit drm_mode_config_cleanup")
+Signed-off-by: Pan Bian <bianpan2016@163.com>
+Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/imx/imx-drm-core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/imx/imx-drm-core.c
++++ b/drivers/gpu/drm/imx/imx-drm-core.c
+@@ -215,7 +215,7 @@ static int imx_drm_bind(struct device *d
+
+ ret = drmm_mode_config_init(drm);
+ if (ret)
+- return ret;
++ goto err_kms;
+
+ ret = drm_vblank_init(drm, MAX_CRTC);
+ if (ret)
--- /dev/null
+From a31500fe7055451ed9043c8fff938dfa6f70ee37 Mon Sep 17 00:00:00 2001
+From: Thierry Reding <treding@nvidia.com>
+Date: Fri, 19 Mar 2021 08:06:37 +0100
+Subject: drm/tegra: dc: Restore coupling of display controllers
+
+From: Thierry Reding <treding@nvidia.com>
+
+commit a31500fe7055451ed9043c8fff938dfa6f70ee37 upstream.
+
+Coupling of display controllers used to rely on runtime PM to take the
+companion controller out of reset. Commit fd67e9c6ed5a ("drm/tegra: Do
+not implement runtime PM") accidentally broke this when runtime PM was
+removed.
+
+Restore this functionality by reusing the hierarchical host1x client
+suspend/resume infrastructure that's similar to runtime PM and which
+perfectly fits this use-case.
+
+Fixes: fd67e9c6ed5a ("drm/tegra: Do not implement runtime PM")
+Reported-by: Dmitry Osipenko <digetx@gmail.com>
+Reported-by: Paul Fertser <fercerpav@gmail.com>
+Tested-by: Dmitry Osipenko <digetx@gmail.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/tegra/dc.c | 20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+--- a/drivers/gpu/drm/tegra/dc.c
++++ b/drivers/gpu/drm/tegra/dc.c
+@@ -2501,22 +2501,18 @@ static int tegra_dc_couple(struct tegra_
+ * POWER_CONTROL registers during CRTC enabling.
+ */
+ if (dc->soc->coupled_pm && dc->pipe == 1) {
+- u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER;
+- struct device_link *link;
+- struct device *partner;
++ struct device *companion;
++ struct tegra_dc *parent;
+
+- partner = driver_find_device(dc->dev->driver, NULL, NULL,
+- tegra_dc_match_by_pipe);
+- if (!partner)
++ companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
++ tegra_dc_match_by_pipe);
++ if (!companion)
+ return -EPROBE_DEFER;
+
+- link = device_link_add(dc->dev, partner, flags);
+- if (!link) {
+- dev_err(dc->dev, "failed to link controllers\n");
+- return -EINVAL;
+- }
++ parent = dev_get_drvdata(companion);
++ dc->client.parent = &parent->client;
+
+- dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner));
++ dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
+ }
+
+ return 0;
--- /dev/null
+From ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 Mon Sep 17 00:00:00 2001
+From: Thierry Reding <treding@nvidia.com>
+Date: Fri, 19 Mar 2021 14:17:22 +0100
+Subject: drm/tegra: sor: Grab runtime PM reference across reset
+
+From: Thierry Reding <treding@nvidia.com>
+
+commit ac097aecfef0bb289ca53d2fe0b73fc7e1612a05 upstream.
+
+The SOR resets are exclusively shared with the SOR power domain. This
+means that exclusive access can only be granted temporarily and in order
+for that to work, a rigorous sequence must be observed. To ensure that a
+single consumer gets exclusive access to a reset, each consumer must
+implement a rigorous protocol using the reset_control_acquire() and
+reset_control_release() functions.
+
+However, these functions alone don't provide any guarantees at the
+system level. Drivers need to ensure that the only a single consumer has
+access to the reset at the same time. In order for the SOR to be able to
+exclusively access its reset, it must therefore ensure that the SOR
+power domain is not powered off by holding on to a runtime PM reference
+to that power domain across the reset assert/deassert operation.
+
+This used to work fine by accident, but was revealed when recently more
+devices started to rely on the SOR power domain.
+
+Fixes: 11c632e1cfd3 ("drm/tegra: sor: Implement acquire/release for reset")
+Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/tegra/sor.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/tegra/sor.c
++++ b/drivers/gpu/drm/tegra/sor.c
+@@ -3115,6 +3115,12 @@ static int tegra_sor_init(struct host1x_
+ * kernel is possible.
+ */
+ if (sor->rst) {
++ err = pm_runtime_resume_and_get(sor->dev);
++ if (err < 0) {
++ dev_err(sor->dev, "failed to get runtime PM: %d\n", err);
++ return err;
++ }
++
+ err = reset_control_acquire(sor->rst);
+ if (err < 0) {
+ dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
+@@ -3148,6 +3154,7 @@ static int tegra_sor_init(struct host1x_
+ }
+
+ reset_control_release(sor->rst);
++ pm_runtime_put(sor->dev);
+ }
+
+ err = clk_prepare_enable(sor->clk_safe);
--- /dev/null
+From 5d5f2919273d1089a00556cad68e7f462f3dd2eb Mon Sep 17 00:00:00 2001
+From: Lars Povlsen <lars.povlsen@microchip.com>
+Date: Wed, 3 Feb 2021 13:38:25 +0100
+Subject: pinctrl: microchip-sgpio: Fix wrong register offset for IRQ trigger
+
+From: Lars Povlsen <lars.povlsen@microchip.com>
+
+commit 5d5f2919273d1089a00556cad68e7f462f3dd2eb upstream.
+
+This patch fixes using a wrong register offset when configuring an IRQ
+trigger type.
+
+Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)")
+Reported-by: Gustavo A. R. Silva <gustavoars@kernel.org>
+Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
+Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
+Link: https://lore.kernel.org/r/20210203123825.611576-1-lars.povlsen@microchip.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/pinctrl-microchip-sgpio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-microchip-sgpio.c
++++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
+@@ -572,7 +572,7 @@ static void microchip_sgpio_irq_settype(
+ /* Type value spread over 2 registers sets: low, high bit */
+ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
+ BIT(addr.port), (!!(type & 0x1)) << addr.port);
+- sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
++ sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
+ BIT(addr.port), (!!(type & 0x2)) << addr.port);
+
+ if (type == SGPIO_INT_TRG_LEVEL)
--- /dev/null
+From 58b5ada8c465b5f1300bc021ebd3d3b8149124b4 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Tue, 23 Mar 2021 14:17:13 +0100
+Subject: pinctrl: qcom: fix unintentional string concatenation
+
+From: Arnd Bergmann <arnd@arndb.de>
+
+commit 58b5ada8c465b5f1300bc021ebd3d3b8149124b4 upstream.
+
+clang is clearly correct to point out a typo in a silly
+array of strings:
+
+drivers/pinctrl/qcom/pinctrl-sdx55.c:426:61: error: suspicious concatenation of string literals in an array initialization; did you mean to separate the elements with a comma? [-Werror,-Wstring-concatenation]
+ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22",
+ ^
+Add the missing comma that must have accidentally been removed.
+
+Fixes: ac43c44a7a37 ("pinctrl: qcom: Add SDX55 pincontrol driver")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Reviewed-by: Nathan Chancellor <nathan@kernel.org>
+Link: https://lore.kernel.org/r/20210323131728.2702789-1-arnd@kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/qcom/pinctrl-sdx55.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/qcom/pinctrl-sdx55.c
++++ b/drivers/pinctrl/qcom/pinctrl-sdx55.c
+@@ -423,7 +423,7 @@ static const char * const gpio_groups[]
+
+ static const char * const qdss_stm_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13",
+- "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19" "gpio20", "gpio21", "gpio22",
++ "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+ "gpio23", "gpio44", "gpio45", "gpio52", "gpio53", "gpio56", "gpio57", "gpio61", "gpio62",
+ "gpio63", "gpio64", "gpio65", "gpio66",
+ };
--- /dev/null
+From 2a9be38099e338f597c14d3cb851849b01db05f6 Mon Sep 17 00:00:00 2001
+From: Jonathan Marek <jonathan@marek.ca>
+Date: Thu, 4 Mar 2021 14:48:16 -0500
+Subject: pinctrl: qcom: lpass lpi: use default pullup/strength values
+
+From: Jonathan Marek <jonathan@marek.ca>
+
+commit 2a9be38099e338f597c14d3cb851849b01db05f6 upstream.
+
+If these fields are not set in dts, the driver will use these variables
+uninitialized to set the fields. Not only will it set garbage values for
+these fields, but it can overflow into other fields and break those.
+
+In the current sm8250 dts, the dmic01 entries do not have a pullup setting,
+and might not work without this change.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
+Signed-off-by: Jonathan Marek <jonathan@marek.ca>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20210304194816.3843-1-jonathan@marek.ca
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
++++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+@@ -392,7 +392,7 @@ static int lpi_config_set(struct pinctrl
+ unsigned long *configs, unsigned int nconfs)
+ {
+ struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
+- unsigned int param, arg, pullup, strength;
++ unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
+ bool value, output_enabled = false;
+ const struct lpi_pingroup *g;
+ unsigned long sval;
--- /dev/null
+From d0f9f47c07fe52b34e2ff8590cf09e0a9d8d6f99 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@codeaurora.org>
+Date: Tue, 2 Mar 2021 10:51:51 +0530
+Subject: pinctrl: qcom: sc7280: Fix SDC1_RCLK configurations
+
+From: Rajendra Nayak <rnayak@codeaurora.org>
+
+commit d0f9f47c07fe52b34e2ff8590cf09e0a9d8d6f99 upstream.
+
+Fix SDC1_RCLK configurations which are in a different register so fix the
+offset from 0xb3000 to 0xb3004.
+
+Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
+Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
+Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
+Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/1614662511-26519-2-git-send-email-rnayak@codeaurora.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/qcom/pinctrl-sc7280.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
++++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
+@@ -1440,7 +1440,7 @@ static const struct msm_pingroup sc7280_
+ [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
+ [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
+ [175] = UFS_RESET(ufs_reset, 0xbe000),
+- [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3000, 15, 0),
++ [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6),
+ [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6),
+ [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3),
+ [179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0),
--- /dev/null
+From 07abd8db9358751107cc46d1cdbd44a92c76a934 Mon Sep 17 00:00:00 2001
+From: Rajendra Nayak <rnayak@codeaurora.org>
+Date: Tue, 2 Mar 2021 10:51:50 +0530
+Subject: pinctrl: qcom: sc7280: Fix SDC_QDSD_PINGROUP and UFS_RESET offsets
+
+From: Rajendra Nayak <rnayak@codeaurora.org>
+
+commit 07abd8db9358751107cc46d1cdbd44a92c76a934 upstream.
+
+The offsets for SDC_QDSD_PINGROUP and UFS_RESET were off by 0x100000
+due to an issue in the scripts generating the data.
+
+Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
+Reported-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org>
+Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
+Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/1614662511-26519-1-git-send-email-rnayak@codeaurora.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/qcom/pinctrl-sc7280.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
++++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
+@@ -1439,14 +1439,14 @@ static const struct msm_pingroup sc7280_
+ [172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _),
+ [173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
+ [174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
+- [175] = UFS_RESET(ufs_reset, 0x1be000),
+- [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
+- [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
+- [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
+- [179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
+- [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
+- [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
+- [182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
++ [175] = UFS_RESET(ufs_reset, 0xbe000),
++ [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3000, 15, 0),
++ [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6),
++ [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3),
++ [179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0),
++ [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0xb4000, 14, 6),
++ [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xb4000, 11, 3),
++ [182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0),
+ };
+
+ static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
--- /dev/null
+From c971af25cda94afe71617790826a86253e88eab0 Mon Sep 17 00:00:00 2001
+From: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+Date: Tue, 23 Feb 2021 18:07:25 +0800
+Subject: pinctrl: rockchip: fix restore error in resume
+
+From: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+
+commit c971af25cda94afe71617790826a86253e88eab0 upstream.
+
+The restore in resume should match to suspend which only set for RK3288
+SoCs pinctrl.
+
+Fixes: 8dca933127024 ("pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume")
+Reviewed-by: Jianqun Xu <jay.xu@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
+Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
+Link: https://lore.kernel.org/r/20210223100725.269240-1-jay.xu@rock-chips.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pinctrl/pinctrl-rockchip.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -3727,12 +3727,15 @@ static int __maybe_unused rockchip_pinct
+ static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
+ {
+ struct rockchip_pinctrl *info = dev_get_drvdata(dev);
+- int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
+- rk3288_grf_gpio6c_iomux |
+- GPIO6C6_SEL_WRITE_ENABLE);
++ int ret;
+
+- if (ret)
+- return ret;
++ if (info->ctrl->type == RK3288) {
++ ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
++ rk3288_grf_gpio6c_iomux |
++ GPIO6C6_SEL_WRITE_ENABLE);
++ if (ret)
++ return ret;
++ }
+
+ return pinctrl_force_default(info->pctl_dev);
+ }
drm-amdgpu-set-a-suitable-dev_info.gart_page_size.patch
drm-amdgpu-check-alignment-on-cpu-page-for-bo-map.patch
reiserfs-update-reiserfs_xattrs_initialized-condition.patch
+drm-imx-fix-memory-leak-when-fails-to-init.patch
+drm-tegra-dc-restore-coupling-of-display-controllers.patch
+drm-tegra-sor-grab-runtime-pm-reference-across-reset.patch
+vfio-nvlink-add-missing-spapr_tce_iommu-depends.patch
+pinctrl-microchip-sgpio-fix-wrong-register-offset-for-irq-trigger.patch
+pinctrl-rockchip-fix-restore-error-in-resume.patch
+pinctrl-qcom-sc7280-fix-sdc_qdsd_pingroup-and-ufs_reset-offsets.patch
+pinctrl-qcom-sc7280-fix-sdc1_rclk-configurations.patch
+pinctrl-qcom-lpass-lpi-use-default-pullup-strength-values.patch
+pinctrl-qcom-fix-unintentional-string-concatenation.patch
--- /dev/null
+From e0146a108ce4d2c22b9510fd12268e3ee72a0161 Mon Sep 17 00:00:00 2001
+From: Jason Gunthorpe <jgg@nvidia.com>
+Date: Mon, 29 Mar 2021 16:00:16 -0300
+Subject: vfio/nvlink: Add missing SPAPR_TCE_IOMMU depends
+
+From: Jason Gunthorpe <jgg@nvidia.com>
+
+commit e0146a108ce4d2c22b9510fd12268e3ee72a0161 upstream.
+
+Compiling the nvlink stuff relies on the SPAPR_TCE_IOMMU otherwise there
+are compile errors:
+
+ drivers/vfio/pci/vfio_pci_nvlink2.c:101:10: error: implicit declaration of function 'mm_iommu_put' [-Werror,-Wimplicit-function-declaration]
+ ret = mm_iommu_put(data->mm, data->mem);
+
+As PPC only defines these functions when the config is set.
+
+Previously this wasn't a problem by chance as SPAPR_TCE_IOMMU was the only
+IOMMU that could have satisfied IOMMU_API on POWERNV.
+
+Fixes: 179209fa1270 ("vfio: IOMMU_API should be selected")
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
+Message-Id: <0-v1-83dba9768fc3+419-vfio_nvlink2_kconfig_jgg@nvidia.com>
+Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/vfio/pci/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/vfio/pci/Kconfig
++++ b/drivers/vfio/pci/Kconfig
+@@ -42,7 +42,7 @@ config VFIO_PCI_IGD
+
+ config VFIO_PCI_NVLINK2
+ def_bool y
+- depends on VFIO_PCI && PPC_POWERNV
++ depends on VFIO_PCI && PPC_POWERNV && SPAPR_TCE_IOMMU
+ help
+ VFIO PCI support for P9 Witherspoon machine with NVIDIA V100 GPUs
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
