clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch

The ECPRI clock controller’s mem_ops clocks used the mem_enable_ack_mask
directly for both setting and polling.
Add the newly introduced 'mem_enable_mask' to the memory control branch
clocks of ECPRI clock controller to align to the new mem_ops handling.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/ecpricc-qdu1000.c b/drivers/clk/qcom/ecpricc-qdu1000.c
index dbc11260479b6d25d52a7d00cfce78d4e35be224..c2a16616ed64508355a3d54557295cef24dfdf2f 100644 (file)
--- a/drivers/clk/qcom/ecpricc-qdu1000.c
+++ b/drivers/clk/qcom/ecpricc-qdu1000.c
@@ -920,6 +920,7 @@ static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
        .mem_enable_reg = 0x8410,
        .mem_ack_reg = 0x8424,
+       .mem_enable_mask = BIT(0),
        .mem_enable_ack_mask = BIT(0),
        .branch = {
                .halt_reg = 0x80b4,
@@ -943,6 +944,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
        .mem_enable_reg = 0x8410,
        .mem_ack_reg = 0x8424,
+       .mem_enable_mask = BIT(1),
        .mem_enable_ack_mask = BIT(1),
        .branch = {
                .halt_reg = 0x80bc,
@@ -966,6 +968,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
        .mem_enable_reg = 0x8410,
        .mem_ack_reg = 0x8424,
+       .mem_enable_mask = BIT(4),
        .mem_enable_ack_mask = BIT(4),
        .branch = {
                .halt_reg = 0x80ac,
@@ -989,6 +992,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
        .mem_enable_reg = 0x8414,
        .mem_ack_reg = 0x8428,
+       .mem_enable_mask = BIT(0),
        .mem_enable_ack_mask = BIT(0),
        .branch = {
                .halt_reg = 0x80d8,
@@ -1012,6 +1016,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {
        .mem_enable_reg = 0x8414,
        .mem_ack_reg = 0x8428,
+       .mem_enable_mask = BIT(1),
        .mem_enable_ack_mask = BIT(1),
        .branch = {
                .halt_reg = 0x80e0,
@@ -1053,6 +1058,7 @@ static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(0),
        .mem_enable_ack_mask = BIT(0),
        .branch = {
                .halt_reg = 0x800c,
@@ -1076,6 +1082,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(1),
        .mem_enable_ack_mask = BIT(1),
        .branch = {
                .halt_reg = 0x8014,
@@ -1099,6 +1106,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(2),
        .mem_enable_ack_mask = BIT(2),
        .branch = {
                .halt_reg = 0x801c,
@@ -1122,6 +1130,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(3),
        .mem_enable_ack_mask = BIT(3),
        .branch = {
                .halt_reg = 0x8024,
@@ -1163,6 +1172,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(0),
        .mem_enable_ack_mask = BIT(0),
        .branch = {
                .halt_reg = 0x8044,
@@ -1186,6 +1196,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(1),
        .mem_enable_ack_mask = BIT(1),
        .branch = {
                .halt_reg = 0x804c,
@@ -1209,6 +1220,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(2),
        .mem_enable_ack_mask = BIT(2),
        .branch = {
                .halt_reg = 0x8054,
@@ -1232,6 +1244,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(3),
        .mem_enable_ack_mask = BIT(3),
        .branch = {
                .halt_reg = 0x805c,
@@ -1273,6 +1286,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(0),
        .mem_enable_ack_mask = BIT(0),
        .branch = {
                .halt_reg = 0x807c,
@@ -1296,6 +1310,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(1),
        .mem_enable_ack_mask = BIT(1),
        .branch = {
                .halt_reg = 0x8084,
@@ -1319,6 +1334,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(2),
        .mem_enable_ack_mask = BIT(2),
        .branch = {
                .halt_reg = 0x808c,
@@ -1342,6 +1358,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(3),
        .mem_enable_ack_mask = BIT(3),
        .branch = {
                .halt_reg = 0x8094,
@@ -1383,6 +1400,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(4),
        .mem_enable_ack_mask = BIT(4),
        .branch = {
                .halt_reg = 0x8004,
@@ -1406,6 +1424,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(4),
        .mem_enable_ack_mask = BIT(4),
        .branch = {
                .halt_reg = 0x803c,
@@ -1429,6 +1448,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(4),
        .mem_enable_ack_mask = BIT(4),
        .branch = {
                .halt_reg = 0x8074,
@@ -1452,6 +1472,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
        .mem_enable_reg = 0x8410,
        .mem_ack_reg = 0x8424,
+       .mem_enable_mask = BIT(5),
        .mem_enable_ack_mask = BIT(5),
        .branch = {
                .halt_reg = 0x80c4,
@@ -1475,6 +1496,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
        .mem_enable_reg = 0x8414,
        .mem_ack_reg = 0x8428,
+       .mem_enable_mask = BIT(5),
        .mem_enable_ack_mask = BIT(5),
        .branch = {
                .halt_reg = 0x80e8,
@@ -1498,6 +1520,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(5),
        .mem_enable_ack_mask = BIT(5),
        .branch = {
                .halt_reg = 0x802c,
@@ -1521,6 +1544,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841c,
+       .mem_enable_mask = BIT(5),
        .mem_enable_ack_mask = BIT(5),
        .branch = {
                .halt_reg = 0x8064,
@@ -1544,6 +1568,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
 static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(5),
        .mem_enable_ack_mask = BIT(5),
        .branch = {
                .halt_reg = 0x809c,
@@ -1603,6 +1628,7 @@ static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = {
 static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
        .mem_enable_reg = 0x8404,
        .mem_ack_reg = 0x8418,
+       .mem_enable_mask = BIT(6),
        .mem_enable_ack_mask = BIT(6),
        .branch = {
                .halt_reg = 0xd140,
@@ -1621,6 +1647,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
 static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
        .mem_enable_reg = 0x8408,
        .mem_ack_reg = 0x841C,
+       .mem_enable_mask = BIT(6),
        .mem_enable_ack_mask = BIT(6),
        .branch = {
                .halt_reg = 0xd148,
@@ -1639,6 +1666,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
 static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
        .mem_enable_reg = 0x840c,
        .mem_ack_reg = 0x8420,
+       .mem_enable_mask = BIT(6),
        .mem_enable_ack_mask = BIT(6),
        .branch = {
                .halt_reg = 0xd150,
@@ -1657,6 +1685,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
 static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
        .mem_enable_reg = 0x8410,
        .mem_ack_reg = 0x8424,
+       .mem_enable_mask = BIT(6),
        .mem_enable_ack_mask = BIT(6),
        .branch = {
                .halt_reg = 0xd158,
@@ -1675,6 +1704,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
 static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {
        .mem_enable_reg = 0x8414,
        .mem_ack_reg = 0x8428,
+       .mem_enable_mask = BIT(6),
        .mem_enable_ack_mask = BIT(6),
        .branch = {
                .halt_reg = 0xd160,