media: iris: enable support for SC7280 platform

As a part of migrating code from the old Venus driver to the new Iris
one, add support for the SC7280 platform. It is very similar to SM8250,
but it (currently) uses no reset controls (there is an optional
GCC-generated reset, it will be added later) and no AON registers
region. Extend the VPU ops to support optional clocks and skip the AON
shutdown for this platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
index 5ffc1874e8c6362b1c650e912c230e9c4e3bd160..8d8cdb56a3c7722c06287d4d10feed14ba2b254c 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -42,6 +42,7 @@ enum pipe_type {
 };
 
 extern const struct iris_platform_data qcs8300_data;
+extern const struct iris_platform_data sc7280_data;
 extern const struct iris_platform_data sm8250_data;
 extern const struct iris_platform_data sm8550_data;
 extern const struct iris_platform_data sm8650_data;
@@ -50,7 +51,9 @@ extern const struct iris_platform_data sm8750_data;
 enum platform_clk_type {
        IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
        IRIS_CTRL_CLK,
+       IRIS_AHB_CLK,
        IRIS_HW_CLK,
+       IRIS_HW_AHB_CLK,
        IRIS_AXI1_CLK,
        IRIS_CTRL_FREERUN_CLK,
        IRIS_HW_FREERUN_CLK,
@@ -224,6 +227,7 @@ struct iris_platform_data {
        u32 hw_response_timeout;
        struct ubwc_config_data *ubwc_config;
        u32 num_vpp_pipe;
+       bool no_aon;
        u32 max_session_count;
        /* max number of macroblocks per frame supported */
        u32 max_core_mbpf;

diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
index 805179fba0c41bd7c9e3e5de365912de2b56c182..34cbeb8f52e248b6aec3e0ee911e14d50df07cce 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c
@@ -12,6 +12,8 @@
 #include "iris_vpu_buffer.h"
 #include "iris_vpu_common.h"
 
+#include "iris_platform_sc7280.h"
+
 #define BITRATE_MIN            32000
 #define BITRATE_MAX            160000000
 #define BITRATE_PEAK_DEFAULT   (BITRATE_DEFAULT * 2)
@@ -362,3 +364,54 @@ const struct iris_platform_data sm8250_data = {
        .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
        .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
 };
+
+const struct iris_platform_data sc7280_data = {
+       .get_instance = iris_hfi_gen1_get_instance,
+       .init_hfi_command_ops = &iris_hfi_gen1_command_ops_init,
+       .init_hfi_response_ops = iris_hfi_gen1_response_ops_init,
+       .get_vpu_buffer_size = iris_vpu_buf_size,
+       .vpu_ops = &iris_vpu2_ops,
+       .set_preset_registers = iris_set_sm8250_preset_registers,
+       .icc_tbl = sm8250_icc_table,
+       .icc_tbl_size = ARRAY_SIZE(sm8250_icc_table),
+       .bw_tbl_dec = sc7280_bw_table_dec,
+       .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
+       .pmdomain_tbl = sm8250_pmdomain_table,
+       .pmdomain_tbl_size = ARRAY_SIZE(sm8250_pmdomain_table),
+       .opp_pd_tbl = sc7280_opp_pd_table,
+       .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
+       .clk_tbl = sc7280_clk_table,
+       .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
+       /* Upper bound of DMA address range */
+       .dma_mask = 0xe0000000 - 1,
+       .fwname = "qcom/vpu/vpu20_p1.mbn",
+       .pas_id = IRIS_PAS_ID,
+       .inst_caps = &platform_inst_cap_sm8250,
+       .inst_fw_caps_dec = inst_fw_cap_sm8250_dec,
+       .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8250_dec),
+       .inst_fw_caps_enc = inst_fw_cap_sm8250_enc,
+       .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8250_enc),
+       .tz_cp_config_data = &tz_cp_config_sm8250,
+       .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
+       .num_vpp_pipe = 1,
+       .no_aon = true,
+       .max_session_count = 16,
+       .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
+       /* max spec for SC7280 is 4096x2176@60fps */
+       .max_core_mbps = 4096 * 2176 / 256 * 60,
+       .dec_input_config_params_default =
+               sm8250_vdec_input_config_param_default,
+       .dec_input_config_params_default_size =
+               ARRAY_SIZE(sm8250_vdec_input_config_param_default),
+       .enc_input_config_params = sm8250_venc_input_config_param,
+       .enc_input_config_params_size =
+               ARRAY_SIZE(sm8250_venc_input_config_param),
+
+       .dec_ip_int_buf_tbl = sm8250_dec_ip_int_buf_tbl,
+       .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl),
+       .dec_op_int_buf_tbl = sm8250_dec_op_int_buf_tbl,
+       .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8250_dec_op_int_buf_tbl),
+
+       .enc_ip_int_buf_tbl = sm8250_enc_ip_int_buf_tbl,
+       .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl),
+};

diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
new file mode 100644 (file)
index 0000000..f1bef4d
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __IRIS_PLATFORM_SC7280_H__
+#define __IRIS_PLATFORM_SC7280_H__
+
+static const struct bw_info sc7280_bw_table_dec[] = {
+       { ((3840 * 2160) / 256) * 60, 1896000, },
+       { ((3840 * 2160) / 256) * 30,  968000, },
+       { ((1920 * 1080) / 256) * 60,  618000, },
+       { ((1920 * 1080) / 256) * 30,  318000, },
+};
+
+static const char * const sc7280_opp_pd_table[] = { "cx" };
+
+static const struct platform_clk_data sc7280_clk_table[] = {
+       {IRIS_CTRL_CLK,    "core"         },
+       {IRIS_AXI_CLK,     "iface"        },
+       {IRIS_AHB_CLK,     "bus"          },
+       {IRIS_HW_CLK,      "vcodec_core"  },
+       {IRIS_HW_AHB_CLK,  "vcodec_bus"   },
+};
+
+#endif

diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
index 00e99be16e087c4098f930151fd76cd381d721ce..9bc9b34c2576581635fa8d87eed1965657eb3eb3 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_probe.c
+++ b/drivers/media/platform/qcom/iris/iris_probe.c
@@ -357,6 +357,10 @@ static const struct of_device_id iris_dt_match[] = {
                .data = &qcs8300_data,
        },
 #if (!IS_ENABLED(CONFIG_VIDEO_QCOM_VENUS))
+       {
+               .compatible = "qcom,sc7280-venus",
+               .data = &sc7280_data,
+       },
        {
                .compatible = "qcom,sm8250-venus",
                .data = &sm8250_data,

diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/media/platform/qcom/iris/iris_resources.c
index cf32f268b703c1c042a9bcf146e444fff4f4990d..164490c49c95ee048670981fdab014d20436ef85 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_resources.c
+++ b/drivers/media/platform/qcom/iris/iris_resources.c
@@ -112,7 +112,7 @@ int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_type clk
 
        clock = iris_get_clk_by_type(core, clk_type);
        if (!clock)
-               return -EINVAL;
+               return -ENOENT;
 
        return clk_prepare_enable(clock);
 }

diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c
index de7d142316d2dc9ab0c4ad9cc8161c87ac949b4c..9c103a2e4e4eafee101a8a9b168fdc8ca76e277d 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_vpu2.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu2.c
@@ -3,9 +3,15 @@
  * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <linux/bits.h>
+#include <linux/iopoll.h>
+#include <linux/reset.h>
+
 #include "iris_instance.h"
 #include "iris_vpu_common.h"
 
+#include "iris_vpu_register_defines.h"
+
 static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size)
 {
        struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;

diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..515dd55a3377e5d4d131e360f361a44a0a92505b 100644 (file)
--- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
+++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
@@ -222,12 +222,14 @@ int iris_vpu_power_off_controller(struct iris_core *core)
 
        writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
 
-       writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
+       if (!core->iris_platform_data->no_aon) {
+               writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
 
-       ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
-                                val, val & BIT(0), 200, 2000);
-       if (ret)
-               goto disable_power;
+               ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
+                                        val, val & BIT(0), 200, 2000);
+               if (ret)
+                       goto disable_power;
+       }
 
        writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
 
@@ -250,6 +252,7 @@ int iris_vpu_power_off_controller(struct iris_core *core)
        writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG);
 
 disable_power:
+       iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
        iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
        iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
        iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -261,6 +264,7 @@ void iris_vpu_power_off_hw(struct iris_core *core)
 {
        dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
        iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
+       iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
        iris_disable_unprepare_clock(core, IRIS_HW_CLK);
 }
 
@@ -294,11 +298,17 @@ int iris_vpu_power_on_controller(struct iris_core *core)
 
        ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
        if (ret)
-               goto err_disable_clock;
+               goto err_disable_axi_clock;
+
+       ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK);
+       if (ret && ret != -ENOENT)
+               goto err_disable_ctrl_clock;
 
        return 0;
 
-err_disable_clock:
+err_disable_ctrl_clock:
+       iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
+err_disable_axi_clock:
        iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
 err_disable_power:
        iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
@@ -318,13 +328,19 @@ int iris_vpu_power_on_hw(struct iris_core *core)
        if (ret)
                goto err_disable_power;
 
+       ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
+       if (ret && ret != -ENOENT)
+               goto err_disable_hw_clock;
+
        ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);
        if (ret)
-               goto err_disable_clock;
+               goto err_disable_hw_ahb_clock;
 
        return 0;
 
-err_disable_clock:
+err_disable_hw_ahb_clock:
+       iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
+err_disable_hw_clock:
        iris_disable_unprepare_clock(core, IRIS_HW_CLK);
 err_disable_power:
        iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);