ARM: dts: Reconfigure the MC2 eMMC interface

The eMMC interface was configured to configure the FBCLK
into the Alt A setting, but this should be in GPIO mode
and available for use as a reset line. Move it to the new
mc_a_2 setting, and define this config in the generic
options.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-ux500-dts-updates-v1-2-a89bfbd0f680@linaro.org

diff --git a/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi
index 31a86606bedaede9539a950c127bcd2b8d03e112..9a6304b7ab2566bc5bac49f13816cb9884398f74 100644 (file)
--- a/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/ste-dbx5x0-pinctrl.dtsi
@@ -454,6 +454,31 @@
                        };
                };
 
+               /* MC2 without feedback clock on A8 */
+               mc2_a_2_default: mc2_a_2_default {
+                       default_mux {
+                               function = "mc2";
+                               groups = "mc2_a_2";
+                       };
+                       default_cfg1 {
+                               pins = "GPIO128_A5"; /* CLK */
+                               ste,config = <&out_lo>;
+                       };
+                       default_cfg2 {
+                               pins =
+                               "GPIO129_B4", /* CMD */
+                               "GPIO131_A12", /* DAT0 */
+                               "GPIO132_C10", /* DAT1 */
+                               "GPIO133_B10", /* DAT2 */
+                               "GPIO134_B9", /* DAT3 */
+                               "GPIO135_A9", /* DAT4 */
+                               "GPIO136_C7", /* DAT5 */
+                               "GPIO137_A7", /* DAT6 */
+                               "GPIO138_C5"; /* DAT7 */
+                               ste,config = <&in_pu>;
+                       };
+               };
+
                mc2_a_1_sleep: mc2_a_1_sleep {
                        sleep_cfg1 {
                                pins = "GPIO128_A5"; /* CLK */
@@ -478,6 +503,30 @@
                                ste,config = <&in_wkup_pdis>;
                        };
                };
+
+               mc2_a_2_sleep: mc2_a_2_sleep {
+                       sleep_cfg1 {
+                               pins = "GPIO128_A5"; /* CLK */
+                               ste,config = <&out_lo_wkup_pdis>;
+                       };
+                       sleep_cfg2 {
+                               pins =
+                               "GPIO129_B4"; /* CMD */
+                               ste,config = <&in_wkup_pdis_en>;
+                       };
+                       sleep_cfg3 {
+                               pins =
+                               "GPIO131_A12", /* DAT0 */
+                               "GPIO132_C10", /* DAT1 */
+                               "GPIO133_B10", /* DAT2 */
+                               "GPIO134_B9", /* DAT3 */
+                               "GPIO135_A9", /* DAT4 */
+                               "GPIO136_C7", /* DAT5 */
+                               "GPIO137_A7", /* DAT6 */
+                               "GPIO138_C5"; /* DAT7 */
+                               ste,config = <&in_wkup_pdis>;
+                       };
+               };
        };
 
        sdi4 {

diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts
index a86e7f7f391fac40f51c1409d1e614b726c481f2..40b0d92dfb1546ed6a8becf607217dcf0d18fe68 100644 (file)
--- a/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts
+++ b/arch/arm/boot/dts/st/ste-ux500-samsung-codina.dts
@@ -451,13 +451,17 @@
                        no-sdio;
                        no-sd;
                        vmmc-supply = <&ldo_3v3_reg>;
+                       vqmmc-supply = <&db8500_vsmps2_reg>;
                        pinctrl-names = "default", "sleep";
                        /*
-                        * GPIO130 will be set to input no pull-up resulting in a resistor
-                        * pulling the reset high and taking the memory out of reset.
+                        * This muxing excludes the feedback clock on GPIO130
+                        * which is instead used for reset of the eMMC.
+                        * GPIO130 will be set to input no pull-up resulting in
+                        * a resistor pulling the reset high and taking the
+                        * memory out of reset.
                         */
-                       pinctrl-0 = <&mc2_a_1_default>;
-                       pinctrl-1 = <&mc2_a_1_sleep>;
+                       pinctrl-0 = <&mc2_a_2_default>;
+                       pinctrl-1 = <&mc2_a_2_sleep>;
                        status = "okay";
                };
 
@@ -678,14 +682,14 @@
        sdi2 {
                /*
                 * This will make the resistor mounted in R0.0 pull up
-                * the reset line and take the eMMC out of reset. On
-                * R0.4 variants, GPIO130 should be set in GPIO mode and
-                * pulled down. (Not connected.)
+                * the reset line and take the eMMC out of reset so set to
+                * GPIO input mode, no pull-up. On R0.4 variants, GPIO130
+                * could be set in GPIO mode and pulled down. (Not connected.)
                 */
-               mc2_a_1_default {
-                       default_cfg2 {
-                               pins = "GPIO130_C8"; /* FBCLK */
-                               ste,config = <&in_nopull>;
+               mc2_a_2_default {
+                       default_cfg3 {
+                               pins = "GPIO130_C8"; /* RST_N */
+                               ste,config = <&gpio_in_nopull>;
                        };
                };
        };