ARM: dts: rockchip: Add SFC for RK3128

Add the Serial Flash Controller and it's pincontrols.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20240606143401.32454-7-knaerzche@gmail.com
[reference HCLK_SFC by its numeric id to prevent conflicts with the
 clock binding/controller changes]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 4ced1f1fabeab689ce6e1d21325c23664d66de0e..5019aae1be328e28bfae90fea52c9bbc7ad6f949 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -425,6 +425,15 @@
                status = "disabled";
        };
 
+       sfc: spi@1020c000 {
+               compatible = "rockchip,sfc";
+               reg = <0x1020c000 0x8000>;
+               interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_SFC>, <&cru 479>;
+               clock-names = "clk_sfc", "hclk_sfc";
+               status = "disabled";
+       };
+
        sdmmc: mmc@10214000 {
                compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
                reg = <0x10214000 0x4000>;
@@ -1196,6 +1205,32 @@
                        };
                };
 
+               sfc {
+                       sfc_bus2: sfc-bus2 {
+                               rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+                                               <1 RK_PD1 3 &pcfg_pull_default>;
+                       };
+
+                       sfc_bus4: sfc-bus4 {
+                               rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
+                                               <1 RK_PD1 3 &pcfg_pull_default>,
+                                               <1 RK_PD2 3 &pcfg_pull_default>,
+                                               <1 RK_PD3 3 &pcfg_pull_default>;
+                       };
+
+                       sfc_clk: sfc-clk {
+                               rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
+                       };
+
+                       sfc_cs0: sfc-cs0 {
+                               rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
+                       };
+
+                       sfc_cs1: sfc-cs1 {
+                               rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
+                       };
+               };
+
                spdif {
                        spdif_tx: spdif-tx {
                                rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;